# US 6,294,462 B1 · Manufacturing method of interconnection layer for semiconductor device

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- Number: US 6,294,462 B1
- Document ID: US6294462B1
- Status: Granted
- Kind: B1
- Application number: 09/129,000
- Filed: 1998-08-04
- Granted: 2001-09-25
- Earliest claimed: 1997-12-22
- Assignees: Hyundai Electronics Industries Co., Ltd.
- Inventors: Sa Kyun Rha
- Web page: https://patentgrep.com/patent/US6294462B1

## CPC

- H10W 20/045: {for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD]}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/039: {also covering sidewalls of the conductive structures}
- H10W 20/043: {for electroplating}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing an interconnection layer for a semiconductor device comprising the steps of forming a conductive pattern near a surface of a semiconductor substrate or on the surface of the semiconductor substrate, forming an insulation layer on a surface of the conductive pattern, forming grooves in the insulation layer exposing portions of the conductive pattern, forming a first barrier layer pattern on an upper surface of the insulation layer and on sidewalls and bottoms of each of the grooves, selectively forming a seed layer on portions of the first barrier layer pattern, selectively forming a copper interconnection layer on the first barrier layer pattern and the seed layer, and forming a second barrier layer on an upper surface and sides of the copper interconnection layer.

## Claims

### Claim 1

A method of manufacturing an interconnection layer for a semiconductor device comprising the steps of:
forming a conductive pattern near a surface of a semiconductor substrate or on the surface of the semiconductor substrate;
forming an insulation layer on a surface of the conductive pattern;
forming cavities in the insulation layer exposing portions of the conductive pattern;
forming a first barrier layer pattern on a surface of the insulation layer and on sidewalls and bottoms of each of the cavities;
selectively forming a seed layer directly on and in contact with portions of the first barrier layer pattern formed on the sidewalls and bottoms of the grooves;
selectively forming a copper interconnection layer on the first barrier layer pattern and the seed layer; and
forming a second barrier layer on an upper surface and sides of the copper interconnection layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the step of forming the conductive pattern forms a diffusion layer in the semiconductor substrate.

### Claim 3 (depends on 2)

The method of claim 2, wherein the step of forming the conductive pattern forms a metal interconnection connected to the diffusion layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the step of forming the conductive pattern forms a gate electrode on the surface of the semiconductor substrate.

### Claim 5 (depends on 4)

The method of claim 4, wherein the step of forming the conductive pattern forms a metal interconnection connected to the gate electrode.

### Claim 6 (depends on 1)

The method of claim 1, wherein the step of forming the conductive pattern forms a bit line on the surface of the semiconductor substrate.

### Claim 7 (depends on 6)

The method of claim 6, wherein the step of forming the conductive pattern also forms a metal interconnection connected to the bit line.

### Claim 8 (depends on 1)

The method of claim 1, wherein the step of selectively forming the seed layer forms a layer of at least one of nitrated titanium, tungsten, and copper.

### Claim 9 (depends on 8)

The method of claim 8, wherein the step of selectively forming the seed layer forms a layer having a thickness of 500 Å or less.

### Claim 10 (depends on 1)

The method of claim 1, wherein the step of forming the first barrier layer pattern forms a layer of at least one of Ti, TiN, TaN, TiW, TaW, TiSixYy and TaSixYn.

### Claim 11 (depends on 1)

The method of claim 1, wherein the step of forming the first barrier layer pattern forms two sequentially stacked films each including one of Ti, TiN, TaN, TiW, TaW, TiSixYy and TaSixYn.

### Claim 12 (depends on 1)

The method of claim 1, wherein the step of forming the second barrier layer forms a film of at least one of Ti, TiN, TaN, TiW, TaW, TiSixYy and TaSixYn.

### Claim 13 (depends on 1)

The method of claim 1, wherein the step of forming the second barrier layer pattern forms two sequentially stacked films each including one of Ti, TiN, TaN, TiW, TaW, TiSixYy and TaSixYn films.

### Claim 14 (depends on 1)

The method of claim 1, wherein the step of forming grooves in the insulation layer includes a step of dry etching the insulation layer.

### Claim 15 (depends on 1)

The method of claim 1, wherein the step of selectively forming the copper interconnection layer includes the step of metal organic chemical vapor deposition.

### Claim 16 (depends on 1)

The method of claim 1, wherein the step of selectively forming the copper interconnection layer includes the step of electroplating.

### Claim 17 (depends on 1)

The method of claim 1, wherein the step of forming the second barrier layer on the upper surface and the sides of the copper interconnection layer includes the steps of:
forming a second barrier layer on an upper surface of the copper interconnection layer and on the insulation layer;
forming an etching mask pattern thicker than the copper interconnection layer on a surface of the second barrier layer; and
partially etching and removing the second barrier layer by using the etching mask pattern as a mask.

### Claim 18 (depends on 1)

The method of claim 1, wherein the step of selectively forming the seed layer forms a layer having a thickness of 500 Å or less.

### Claim 19 (depends on 14)

The method of claim 14, wherein the step of selectively forming the seed layer forms a layer having a thickness of 500 Å or less.

### Claim 20 (depends on 1)

The method of claim 1, wherein the step of forming grooves in the insulation layer includes the step of wet etching the insulation layer.

### Claim 21 (depends on 14)

The method of claim 14, wherein the stop of selectively forming the seed layer includes the step of least one of chemical vapor deposition or sputtering.

### Claim 22

A method of manufacturing an interconnection layer for a semiconductor device comprising the steps of:
forming a conductive pattern in a surface of a semiconductor substrate or on the surface of the semiconductor substrate;
forming an insulation layer on an upper surface of the conductive pattern;
forming at least one groove having sidewalls and a bottom in the insulation layer exposing upper surfaces of the conductive pattern;
forming a first barrier layer on an upper surface of the insulation layer and on the sidewalls and bottom of the at least one groove;
selectively forming a seed layer directly on and in contact with portions of a surface of the first barrier layer and the sidewalls and the bottom of the at least one groove;
selectively forming a copper interconnection layer on the first barrier layer and the seed layer; and
forming a second barrier layer on the copper interconnection layer.

### Claim 23 (depends on 22)

The method of claim 22, wherein the step of forming the second barrier layer on the copper interconnection layer includes the steps of:
forming a second barrier layer on a surface of the copper interconnection layer and on the insulation layer;
forming an etching mask pattern thicker than the copper interconnection layer on a surface of the second barrier layer; and
partially etching and removing the second barrier layer by using the etching mask pattern as a mask.

### Claim 24 (depends on 22)

The method of claim 22, wherein the seed layer is deposited by chemical vapor deposition or sputtering.