# US 6,294,436 B1 · Method for fabrication of enlarged stacked capacitors using isotropic etching

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- Number: US 6,294,436 B1
- Document ID: US6294436B1
- Status: Granted
- Kind: B1
- Application number: 09/374,538
- Filed: 1999-08-16
- Granted: 2001-09-25
- Earliest claimed: 1999-08-16
- Assignees: Infineon Technologies AG
- Inventors: Youngjin Park; Heon Lee
- Web page: https://patentgrep.com/patent/US6294436B1

## CPC

- H10B 12/033: {the capacitor extending over the transistor}
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

In accordance with the present invention, a method for expanding holes for the formation of stacked capacitors is described and claimed. The method includes the steps of providing a planarized dielectric layer for forming bottom electrodes of the stacked capacitors, forming a first dielectric layer on the planarized dielectric layer, forming a second dielectric layer on the first dielectric layer. The second dielectric layer is selectively etchable relative to the first dielectric layer. The steps of etching the second dielectric layer to form holes for forming the bottom electrodes and isotropically etching the second dielectric layer to expand the holes for forming the bottom electrodes are also included.

## Claims

### Claim 1

A method for expanding holes for the formation of stacked capacitors comprising the steps of:
providing a planarized dielectric layer for forming bottom electrodes of the stacked capacitors;
forming a first dielectric layer on the planarized dielectric layer;
forming a second dielectric layer on the first dielectric layer, the second dielectric layer being selectively etchable relative to the first dielectric layer;
etching the second dielectric layer to form holes for forming the bottom electrodes; and
isotropically etching the second dielectric layer to expand the holes for forming the bottom electrodes.

### Claim 2 (depends on 1)

The method as recited in claim 1, wherein the first dielectric layer includes one of a nitride and Aluminum oxide and the second dielectric layer includes an oxide.

### Claim 3 (depends on 1)

The method as recited in claim 1, further comprising the steps of:
removing portions of the first dielectric layer in the holes;
depositing a conductive layer in the holes to form the bottom electrode; and
depositing a capacitor dielectric layer on the conductive layer.

### Claim 4 (depends on 1)

The method as recited in claim 1, wherein the step of isotropically etching includes employing one of a wet etch and a chemical dry etch process.

### Claim 5 (depends on 1)

The method as recited in claim 1, wherein the step of isotropically etching includes the step of expanding the holes such that a surface area of the holes is increased by a factor greater than 1.

### Claim 6 (depends on 1)

The method as recited in claim 1, wherein the step of isotropically etching includes the step of expanding the holes such that lateral sidewalls of the second dielectric layer adjacent to the holes are recessed by a distance of at least about one third a minimum feature size for a given technology.

### Claim 7 (depends on 1)

The method as recited in claim 1, wherein the holes are tapered.

### Claim 8 (depends on 1)

The method as recited in claim 1, wherein the step of isotropically etching includes the step of forming a stepped portion in the holes.

### Claim 9

A method for forming stacked capacitors for a semiconductor memory device comprising the steps of:
providing a substrate having a planarized dielectric layer formed on access transistors, the planarized dielectric layer having conductive plugs disposed therein for connecting to the access transistors;
forming a first dielectric layer on a top surface of the planarized dielectric layer;
forming a second dielectric layer which is selectively etchable relative to the first dielectric layer;
patterning holes in the second dielectric layer by selectively etching the second dielectric layer relative to the first dielectric layer; and
isotropically etching the holes in the second dielectric layer to expand the holes to provide an increased surface area within the holes over a surface area formed by the selectively etching the second dielectric layer.

### Claim 10 (depends on 9)

The method as recited in claim 9, wherein the first dielectric layer includes one of a nitride and Aluminum oxide and the second dielectric layer includes an oxide.

### Claim 11 (depends on 9)

The method as recited in claim 9, further comprising the steps of:
removing portions of the first dielectric layer in the holes to expose the conductive plugs;
depositing a conductive layer in the holes to form a bottom electrode for the stacked capacitors; and
depositing a capacitor dielectric layer on the conductive layer.

### Claim 12 (depends on 9)

The method as recited in claim 9, wherein the step of isotropically etching includes employing one of a wet etch and a chemical dry etch process.

### Claim 13 (depends on 9)

The method as recited in claim 9, wherein the step of isotropically etching includes the step of expanding the holes such that lateral sidewalls of the second dielectric layer adjacent to the holes are recessed by a distance of at least about one third a minimum feature size for a given technology.

### Claim 14 (depends on 9)

The method as recited in claim 9, wherein the holes are tapered.

### Claim 15 (depends on 9)

The method as recited in claim 9, wherein the step of isotropically etching includes the step of forming a stepped portion in the holes.

### Claim 16

A method for forming stacked capacitors for a dynamic random access memory device comprising the steps of:
providing a substrate having a planarized glass layer formed on access transistors, the planarized glass layer having conductive plugs disposed therein for connecting to the access transistors;
forming a nitride layer on a top surface of the planarized glass layer;
forming an oxide layer which is selectively etchable relative to the nitride layer;
depositing a resist layer on the oxide layer;
patterning the resist layer by forming openings in the resist over locations for the conductive plugs;
anisotropically etching holes in the oxide layer by selectively etching the oxide layer relative to the nitride layer;
isotropically etching the holes in the oxide layer to expand the holes to provide an increased surface area within the holes over a surface area formed by the selectively etching the oxide layer;
removing the resist layer;
removing portions of the nitride layer in the holes to expose the conductive plugs;
depositing a conductive layer in the holes to form a bottom electrode for the stacked capacitors; and
depositing a capacitor dielectric layer on the conductive layer.

### Claim 17 (depends on 16)

The method as recited in claim 16, wherein the step of isotropically etching includes employing one of a wet etch and a chemical dry etch process.

### Claim 18 (depends on 16)

The method as recited in claim 16, wherein the step of isotropically etching includes the step of expanding the holes such that lateral sidewalls of the oxide layer adjacent to the holes are recessed by a distance of at least about one third a minimum feature size for a given technology.

### Claim 19 (depends on 16)

The method as recited in claim 16, wherein the holes are tapered.

### Claim 20 (depends on 16)

The method as recited in claim 16, wherein the step of isotropically etching includes the step of forming a stepped portion in holes.