Alignment techniques for epitaxial growth processes
AssigneeLucent Technologies Inc.
InventorsRobert Alan Hamm, Rose Fasano Kopf, Christopher James Pinzone, Robert William Ryan, Alaric Tate
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Abstract
The specification describes a lithographic technique in which alignment marks are defined in a first semiconductor layer and the alignment marks are then covered with a protective SiO2 layer. After subsequent semiconductor layer growth steps, which selectively deposit on the former semiconductor layer but not on the protective layer, the alignment marks remain undistorted and visible to the exposure tool for subsequent processing.
Claims11
A process for the manufacture of semiconductor integrated circuit devices which includes at least one lithographic alignment the method comprising:
- a. forming a first semiconductor layer on said substrate,
- b. patterning said first semiconductor layer to form a first device feature,
- c. forming semiconductor alignment marks in said first semiconductor layer,
- d. selectively depositing a protective layer on said alignment marks,
- e. depositing a second semiconductor layer using a process whereby semiconductor material is deposited selectively on said first semiconductor layer while not depositing semiconductor material on said protective layer, and
- f. forming a lithographic mask on said second semiconductor layer using said alignment marks to register said lithographic mask.
A method for the manufacture of heterostructure transistors comprising:
- a. depositing a first III-V semiconductor layer on a semiconductor wafer,
- b. patterning said first III-V semiconductor layer to form at least one sub-collector region on said wafer, and a series of semiconductor alignment marks on said wafer,
- c. selectively depositing a protective layer on said alignment marks,
- d. depositing a III-V semiconductor collector layer using a process whereby semiconductor material is deposited selectively on said first semiconductor layer while not depositing semiconductor material on said protective layer bare,
- e. depositing a III-V semiconductor base layer using a process whereby semiconductor material is deposited selectively on said semiconductor collector layer while not depositing semiconductor material on said protective layer bare,
- f. depositing a III-V semiconductor emitter layer using a process whereby semiconductor material is deposited selectively on said semiconductor base layer while not depositing semiconductor material on said protective layer bare,
- g. depositing a III-V semiconductor emitter contact layer using a process whereby semiconductor material is deposited selectively on said semiconductor emitter layer while not depositing semiconductor material on said protective layer bare,
- h. forming a metal contact layer on said semiconductor emitter contact layer,
- i. forming a lithographic mask on said metal contact layer using said alignment marks to register said lithographic mask.
- j. etching said metal contact layer to form a metal contact,
- k. etching said semiconductor emitter layer using said metal contact as a mask to form an emitter,
- l. forming base contacts to said semiconductor base layer,
- m. masking said semiconductor base layer using said alignment marks to register the mask so that the unmasked portion of said semiconductor base layer is aligned to the sub-collector region,
- n. etching the unmasked portion of said semiconductor base layer and an underlying portion of said semiconductor collector layer to form a base and a collector, and
- o. forming electrical contacts to said sub-collector region, said base and said collector.
Dependencies are inferred from the claim text.