# US 6,293,457 B1 · Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 6,293,457 B1
- Document ID: US6293457B1
- Status: Granted
- Kind: B1
- Application number: 09/590,119
- Filed: 2000-06-08
- Granted: 2001-09-25
- Earliest claimed: 2000-06-08
- Assignees: International Business Machines Corporation
- Inventors: Kamalesh K. Srivastava; Jonathan H. Griffith; Mary C. Cullinan-Scholl; William H. Brearley; Peter C. Wade
- Web page: https://patentgrep.com/patent/US6293457B1

## CPC

- C23F 1/26: for etching refractory metals
- H10W 20/082: {the openings being tapered via holes}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01255: {by using masks}
- H10W 72/019: {of bond pads}
- H10W 72/01955: {by using masks}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/251: {Materials}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- C23F: NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE (working metal by laser beams B23K26/00; desurfacing by applying flames B23K7/00; working of metal by electro-erosion B23H; producing decorative effects by removing surface material, e.g. by engraving, by etching, B44C1/22; electrolytic etching or polishing C25F); INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Form a solder connector on a semiconductor device starting with a first step of forming at least one dielectric layer over a doped semiconductor substrate. Then form a hole through the dielectric layer down to the semiconductor substrate. Form a metal conductor in the hole. Form intermediate layers over the metal conductor and the dielectric layer. Then form a tapered opening down to the surface of the metal conductor. Form BLM layers including a titanium-tungsten (TiW) layer over the metal conductor and the dielectric layer with the remainder of the BLM layers being formed over the TiW layer. Form a mask over the top surface of the BLM layers with a patterning through hole located above the metal conductor exposing a portion of the surface of the BLM layers. Plate a C4 solder bump on the BLM layers in the patterning hole. Remove the mask. Wet etch away the BLM layers aside from the solder bump leaving a residual TiW layer over the dielectric layer. Perform a dry etching process to remove the residual TiW layer aside from the solder bump. Then, end the dry etching when the end point has been reached. Finally, heat the solder bump in a reflow process to form a C4 solder ball.

## Claims

### Claim 1

A method for fabricating a solder connector on a doped semiconductor device with a metal conductor structure formed thereon surrounded by a dielectric layer comprising the following steps:
forming the dielectric layer and the metal conductor structure over the doped semiconductor substrate with the dielectric layer surrounding the metal conductor structure,
forming at least one intermediate layer over the dielectric layer and the metal conductor structure,
forming a hole through the intermediate layer down to the metal conductor structure,
forming solder limiting metallurgy (SLM) layers, having a top surface, the SLM layers including a titanium-tungsten (TiW) layer formed over the metal conductor structure and the intermediate layer with the remainder of the SLM layers being formed over the TiW layer,
forming a mask over the top surface of the SLM layers with a patterning through hole located above the metal conductor structure exposing a portion of the surface of the SLM layers,
plating solder into the patterning through hole over the SLM layers and then removing the mask,
wet etching away the SLM layers aside from the solder leaving a residual TiW layer over the dielectric layer,
performing a dry etching process to remove the residual TiW layer aside from the solder, and
detecting the final end point of etching the residual TiW layer and, then ending the dry etching when the final end point has been reached.

### Claim 2 (depends on 1)

The method of claim 1 including the steps as follows:
forming a blanket silicon oxide layer over the metal conductor structure and the dielectric layer,
forming a silicon nitride layer over the silicon oxide layer, forming a polyimide layer over the silicon nitride layer, and
forming an opening down to the metal conductor structure.

### Claim 3 (depends on 1)

The method of claim 1 wherein the solder limiting metallurgy (SLM) layers have a top surface, and the SLM layers include as follows:
a. the titanium-tungsten (TiW) layer on the bottom,
b. an intermediate SLM layer comprising a chromium/copper (Cr/Cu) layer, and
c. an upper layer comprising a Cu layer.

### Claim 4 (depends on 1)

The method of claim 1 including the steps as follows:
forming a blanket silicon oxide layer over the metal conductor structure and the dielectric layer,
forming a silicon nitride layer over the silicon oxide layer,
forming a polyimide layer over the silicon nitride layer,
forming an opening down to the metal conductor structure,
the solder limiting metallurgy (SLM) layers, having a top surface, the SLM layers including the TiW layer on the bottom, an intermediate SLM layer comprising a Cr/Cu layer and an upper layer comprising a Cu layer.

### Claim 5 (depends on 1)

The method of claim 1 including the solder comprising lead/tin (Pb/Sn) solder.

### Claim 6 (depends on 1)

The method of claim 1 wherein the hole through the intermediate layer is tapered.

### Claim 7 (depends on 1)

The method of claim 1 including the steps as follows:
forming a blanket silicon oxide layer over the metal conductor structure and the dielectric layer,
forming a silicon nitride layer over the silicon oxide layer,
forming a polyimide layer over the silicon nitride layer,
forming an opening down to the metal conductor structure,
the solder limiting metallurgy (SLM) layers, having a top surface, the SLM layers including the TiW layer on the bottom, an intermediate SLM layer comprising a Cr/Cu layer and an upper layer comprising a Cu layer, and
the solder comprising lead/tin (Pb/Sn) solder.

### Claim 8 (depends on 1)

The method of claim 1 including the steps as follows:
forming a blanket silicon oxide layer over the metal conductor structure and the dielectric layer,
forming a silicon nitride layer over the silicon oxide layer,
forming a polyimide layer over the silicon nitride layer, and
forming an opening down to the metal conductor structure,
the solder limiting metallurgy (SLM) layers, having a top surface, the SLM layers including the TiW layer on the bottom, an intermediate SLM layer comprising a Cr/Cu layer and an upper layer comprising a Cu layer, and the hole through the intermediate layer is tapered.

### Claim 9 (depends on 1)

The method of claim 1 including the steps as follows:
forming a blanket silicon oxide layer over the metal conductor structure and the dielectric layer,
forming a silicon nitride layer over the silicon oxide layer,
forming a polyimide layer over the silicon nitride layer,
forming an opening down to the metal conductor structure,
the solder limiting metallurgy (SLM) layers, having a top surface, the SLM layers including the TiW layer on the bottom, an intermediate SLM layer comprising a Cr/Cu layer and an upper layer comprising a Cu layer, and
the solder comprising lead/tin (Pb/Sn) solder, and
the hole through the intermediate layer is tapered.

### Claim 10 (depends on 1)

The method of claim 1 including the step of wet etching away the SLM layers aside from the solder leaving a residual TiW layer over the dielectric layer is achieved by employing an initial step of end point detection by determining when a predetermined minimum impedance is reached.

### Claim 11 (depends on 1)

The method of claim 1 including:
the solder limiting metallurgy (SLM) layers, having a top surface, the SLM layers including the titanium-tungsten (TiW) layer on the bottom, an intermediate SLM layer comprising a chromium/copper (Cr/Cu) layer and an upper layer comprising a Cu layer,
the step of wet etching away the chromium/copper (Cr/Cu) layer and the Cu layer layers aside from the solder leaving a residual TiW layer over the dielectric layer,
followed the step of wet etching TiW to a predetermined thickness of TiW which is terminated by employing initial end point detection of the thickness of the TiW layer,
followed by performing a dry etching process to remove the residual TiW layer aside from the solder, and
then followed by ending the dry etching when a final end point has been reached.

### Claim 12

A method for fabricating a solder connector on a semiconductor device comprising the following steps:
forming at least one dielectric layer over a doped semiconductor substrate,
forming a hole through the dielectric layer down to the semiconductor substrate,
forming a metal conductor structure in the hole,
forming intermediate layers over the metal conductor structure and the dielectric layer,
forming a hole through the intermediate layer down to the metal conductor structure,
forming Ball Limiting Metallurgy (BLM) layers, having a top surface,
the BLM layers including a titanium-tungsten (TiW) layer formed over the metal conductor structure and the dielectric layer with the remainder of the BLM layers being formed over the TiW layer,
forming a mask over the top surface of the BLM layers with a patterning through hole located above the metal conductor structure exposing a portion of the surface of the BLM layers,
plating a solder bump in the patterning hole over the BLM layers, removing the mask,
wet etching away the BLM layers aside from the solder bump leaving a residual TiW layer over the dielectric layer until an initial end point has been reached,
performing a dry etching process to remove the residual TiW layer aside from the solder bump,
then ending the dry etching when an end point has been reached, and heating the solder bump in a reflow process to form a solder ball.

### Claim 13 (depends on 12)

The method of claim 12 including forming intermediate layers by the steps as follows:
forming a blanket silicon oxide layer over the metal conductor structure and the dielectric layer,
forming a silicon nitride layer over the silicon oxide layer,
forming a polyimide layer over the silicon nitride layer, and
forming the opening down to the metal conductor structure.

### Claim 14 (depends on 12)

The method of claim 12 including as follows:
the BLM layers, having a top surface, the BLM layers including the titanium-tungsten (TiW) layer on the bottom, an intermediate BLM layer comprising a chromium/copper (Cr/Cu) layer and an upper layer comprising a Cu layer.

### Claim 15 (depends on 12)

The method of claim 12 including the steps as follows:
forming a blanket silicon oxide layer over the metal conductor structure and the dielectric layer,
forming a silicon nitride layer over the silicon oxide layer,
forming a polyimide layer over the silicon nitride layer, and
forming an opening down to the metal conductor structure, and the BLM layers, having a top surface, the BLM layers including the TiW layer on the bottom, an intermediate BLM layer comprising a Cr/Cu layer and an upper layer comprising a Cu layer.

### Claim 16 (depends on 12)

The method of claim 12 wherein the solder comprises lead/tin (Pb/Sn) solder.

### Claim 17 (depends on 12)

The method of claim 12 wherein the hole through the intermediate layer is tapered.

### Claim 18 (depends on 12)

The method of claim 12 including the steps as follows:
forming a blanket silicon oxide layer over the metal conductor structure and the dielectric layer,
forming a silicon nitride layer over the silicon oxide layer,
forming a polyimide layer over the silicon nitride layer,
forming an opening down to the metal conductor structure,
the solder limiting metallurgy BLM layers, having a top surface, the BLM layers including the TiW layer on the bottom, an intermediate BLM layer comprising a Cr/Cu layer and an upper layer comprising a Cu layer, and
the solder comprising lead/tin (Pb/Sn) solder.

### Claim 19 (depends on 12)

The method of claim 12 including the steps as follows:
forming a blanket silicon oxide layer over the metal conductor structure and the dielectric layer,
forming a silicon nitride layer over the silicon oxide layer,
forming a polyimide layer over the silicon nitride layer,
forming an opening down to the metal conductor structure,
the solder limiting metallurgy BLM layers, having a top surface, the BLM layers including the TiW layer on the bottom, an intermediate BLM layer comprising a Cr/Cu layer and an upper layer comprising a Cu layer, and
the hole through the intermediate layer is tapered.

### Claim 20 (depends on 12)

The method of claim 12 including the steps as follows:
forming a blanket silicon oxide layer over the metal conductor structure and the dielectric layer,
forming a silicon nitride layer over the silicon oxide layer,
forming a polyimide layer over the silicon nitride layer,
forming an opening down to the metal conductor structure,
the solder limiting metallurgy BLM layers, having a top surface, the BLM layers including the TiW layer on the bottom, an intermediate BLM layer comprising a Cr/Cu layer and an upper layer comprising a Cu layer,
the solder comprising lead/tin (Pb/Sn) solder, and
the hole through the intermediate layer is tapered.

### Claim 21 (depends on 12)

The method of claim 12 including the step of wet etching away the BLM layers aside from the solder leaving a residual TiW layer over the dielectric layer and terminating the wet etching in response to the results of end point detection indicating that a final end point has been reached when a predetermined minimum impedance is reached.

### Claim 22

A method for fabricating a solder connector on a semiconductor device comprising the following steps:
forming at least one dielectric layer over a doped semiconductor substrate,
forming a hole through the dielectric layer down to the semiconductor substrate,
forming a metal conductor structure in the hole,
forming intermediate layers over the metal conductor structure and the dielectric layer,
forming a hole through the intermediate layer down to the metal conductor structure,
forming Ball Limiting Metallurgy (BLM) layers, having a top surface,
the BLM layers including a titanium-tungsten (TiW) layer formed over the metal conductor structure and the dielectric layer with the remainder of the BLM layers being formed over the TiW layer comprising an intermediate BLM layer comprising a chromium/copper (Cr/Cu) layer and an upper BLM layer comprising a Cu layer, the ball limiting metallurgy (BLM) layers, having a top surface,
forming a mask over the top surface of the BLM layers with a patterning through hole located above the metal conductor structure exposing a portion of the surface of the BLM layers,
plating a solder bump in the patterning hole over the BLM layers, removing the mask,
wet etching away the BLM layers aside from the solder bump leaving a residual TiW layer over the dielectric layer,
performing the step of wet etching away the chromium/copper (Cr/Cu) layer and the Cu layer layers aside from the solder in a potassium sulfate solution leaving a residual TiW layer over the dielectric layer,
then performing the step of wet etching TiW in a wet etching solution of hydrogen peroxide (H2O2), water (H2O), potassium sulfate (K2SO4), sulfuric acid (H2SO4), and EDTA (a salt of EthyleneDiamineTetraAcetic acid) continuing until only a predetermined thickness of TiW remains, at which time the wet etching of TiW is terminated by employing initial end point detection of the residual thickness of the TiW layer,
followed by performing a dry etching process to remove the residual TiW layer aside from the solder bump, and
then ending the dry etching when an end point has been reached, and
heating the solder bump in a reflow process to form a solder ball.

### Claim 23

A method for fabricating a solder connector on a semiconductor device comprising the following steps:
forming at least one dielectric layer over a doped semiconductor substrate,
forming a hole through the dielectric layer down to the semiconductor substrate,
forming a metal conductor structure in the hole,
forming intermediate layers over the metal conductor structure and the dielectric layer,
forming a hole through the intermediate layer down to the metal conductor structure,
forming Ball Limiting Metallurgy (BLM) layers, having a top surface,
the BLM layers including a titanium-tungsten (TiW) layer formed over the metal conductor structure and the dielectric layer with the remainder of the BLM layers being formed over the TiW layer comprising an intermediate BLM layer comprising a chromium/copper (Cr/Cu) layer and an upper BLM layer comprising a Cu layer, the ball limiting metallurgy (BLM) layers, having a top surface,
forming a mask over the top surface of the BLM layers with a patterning through hole located above the metal conductor structure exposing a portion of the surface of the BLM layers,
plating a solder bump in the patterning hole over the BLM layers,
removing the mask,
wet etching away the BLM layers aside from the solder bump leaving a residual TiW layer over the dielectric layer,
performing the step of wet etching away the chromium/copper (Cr/Cu) layer and the Cu layer layers aside from the solder in a potassium sulfate solution leaving a residual TiW layer over the dielectric layer,
then performing the step of wet etching TiW in a wet etching solution of hydrogen peroxide (H2O2), water (H2O), potassium sulfate (K2SO4), sulfuric acid (H2SO4), and EDTA (a salt of EthyleneDiamineTetraAcetic acid) continuing until only a predetermined thickness of TiW remains, at which time the wet etching of TiW is terminated by employing end point detection of the thickness of the TiW layer,
followed by performing a dry etching process to remove the residual TiW layer aside from the solder bump,
then ending the dry etching when an end point has been reached,
heating the solder bump in a reflow process to form a solder ball,
determining when the end point of wet etching of the TiW layer is reached by monitoring the electrical impedance of the TiW layer until a predetermined minimum impedance is reached, and
employing optical detection to determine when all of the TiW layer has been etched away and then terminating the etching operation by controlling a valve between the source of the etchant gases and the workpiece.