Smart memory interface

A data processing system, said data processing system comprising:

• at least one memory device;
• and
• memory control means, said memory control means being responsive to a start-up condition of said system for generating electrical signals to exercise the at least one memory device for setting a timing of said electrical signals so as to enable data to be stored in and read from the at least one memory device without error;
• wherein the electrical signals include first and second electrical signals and wherein the system further comprises:
• circuitry for applying the first electrical signals to the memory control means for generating second electrical signals;
• circuitry for applying the second electrical signals to the memory device;
• circuitry for transferring information between the memory control means and the memory device in accordance with temporal relationships between the second electrical signals;
• circuitry for varying the temporal relationships between first Predetermined ones of the second electrical signals to determine upper and lower bounds of the range within which the temporal relationships need to be set in order for the information to be transferred from the memory device to the memory control means without error;
• and circuitry for setting the temporal relationships between the second electrical signals so as to be between the upper and lower bounds.

A method for transmitting data from a first location to a second location in an electronic system, the method comprising steps of:

• providing at least one clock pulse having a leading pulse edge and a trailing pulse edge from a clock which controls signals at said first location and at said second location;
• transmitting first data from said first location to said second location in accordance with said at least one clock pulse, said first data having a leading edge and a trailing edge, there being a leading phase between said leading edge of said first data and said leading pulse edge, there also being a trailing phase between said trailing edge of said first data and said trailing pulse edge;
• after the first data is received at the second location, transmitting second data from said second location to said first location;
• comparing said first and second data to determine if there are any errors in said second data;
• and
• if there are any errors in said second data, varying said leading phase and said trailing phase to determine values thereof defining a bounded relationship between said at least one clock pulse and said first data within which the first data can be transferred from said first location to said second location substantially without error.

An apparatus for transmitting data from a first location to a second location in an electronic system, said apparatus comprising:

• means for providing at least one clock pulse having a leading pulse edge and a trailing pulse edge from a clock which controls signals at said first location and at said second location;
• means for transmitting first data from said first location to said second location in accordance with said at least one clock pulse, said first data having a leading edge and a trailing edge, there being a leading phase between said leading edge of said first data and said leading pulse edge, there being a trailing phase between said trailing pulse edge and said trailing edge of said first data;
• means for transmitting second data from said second location to said first location;
• means for comparing said first and second data to determine if there are any errors in said second data;
• and
• means for varying said leading phase and said trailing phase to determine values thereof defining a bounded relationship between said at least one clock pulse and said first data within which said first data can be transmitted substantially without error.