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AssigneeInternational Business Machines Corporation
InventorsWolfgang Bultmann, Wilhelm Haller, Holger Wetter, Alexander Wörner
Estimating the term…
A binary and decimal adder unit uses a pre-sum logic for generating pre-sums of the operands A, B under the presumption of one and zero carry inputs into the decimal digit position, and also uses a digits carry network for generating binary carries within the decimal digit positions and a high order carry out signal of said plurality of decimal digits. Each decimal digit position of said adder unit provides a six correction and a pre-sum selection. The pre-sum logic comprises a carry prediction logic for generating decimal digit position carry out signals on the presumption of a zero carry input and of a one carry input into the decimal digit. In response to gating signals derived from the carry out signals of the carry prediction logic and operation control signals a pre-selection is performed for selecting a qualified pre-sum generated on the presumption of a zero carry input into the decimal digit, and for selecting a qualified pre-sum generated on the presumption of a one carry input into the decimal digit. The pre-selection of the qualified pre-sums is performed for all decimal digit positions in parallel to the generation and distribution of the carries in the digits carry network over the total of decimal digit positions. The pre-sum selection logic further comprises a two way selector which is responsive to a digit carry-in signal from the digits carry network for selecting one the qualified pre-sums as the correct sum of the digit position. According to one embodiment of the invention, the pre-sum logic generates six corrected pre-sums which are included in the pre-selection of qualified pre-sums.
A binary and decimal adder unit for processing a plurality of binary or decimal digits with a sum logic for generating binary rough sums of each decimal digit and with a digits carry network (C1) for generating binary carries within the decimal digit positions and a high order carry-out signal of the high order digit position, each decimal digit position of said adder unit comprises a correction logic for performing a six correction, said sum logic comprises a pre-sum logic for generating in each of the decimal digit positions first pre-sums of the operands under the presumption of a carry-in of zero and second pre-sums of the operands under the presumption of a carry-in of one, and said adder unit further comprises a sum selection logic responsive to carry signals from the digit carry logic (C1) and to operation control signals (DEC ADD, DEC SUB) for selecting one of the pre-sums as the correct sum of the digit position,
A method for performing binary and decimal additions of a plurality of binary or decimal digits in a adder unit with a sum logic for generating binary rough sums of each decimal digit and with a digits carry network (C1) for generating binary carries within the decimal digit positions and a high order carry-out signal of the high order digit, each decimal digit position of said adder unit comprises a correction logic for performing a six correction, the method comprising the steps of generating in each of the decimal digit positions first pre-sums of the operands under the presumption of a carry-in of zero and second pre-sums of the operands under the presumption of a carry-in of one, and selecting one of the pre-sums as the correct sum of the digit position in response to carry signals from the digit carry logic (C1) and operation control signals (DEC ADD, DEC SUB),
Dependencies are inferred from the claim text.