Chip-size semiconductor packages

A method of manufacturing a chip-size (CS) ball grid array (BGA), land grid array (LGA), or leadless chip carrier (LCC) semiconductor package from a semiconductor wafer, comprising:

• forming dies in the wafer, each the die being bounded by scribe lines, having a thermal coefficient of expansion (TCE), and a top surface with a plurality of contacts thereon;
• mounting an insulative substrate on each of the die top surfaces, each of the substrate having a plurality of conductors formed on a top surface thereof and a TCE equal to the TCE of the dies, plus or minus 2.5 PPM/° C.;
• electrically connecting first terminals of the plurality of conductors to the contacts with a plurality of electrically conductive connectors;
• encapsulating the plurality of contacts, the plurality of connectors and the first terminals with a protective encapsulant;
• and,
• cutting the wafer along the scribe lines to singulate the dies into individual packages.

A chip-size (CS) semiconductor package, comprising:

• a semiconductor chip having a top surface with a plurality of contacts formed thereon and a thermal coefficient of expansion (TCE);
• an insulative substrate mounted to the top surface of the chip, the substrate having a TCE equal to the TCE of the chip, plus or minus about 2.5 parts-per-million per degree Centigrade (PPM/° C.);
• a plurality of conductors disposed on the substrate, the conductors having first terminals formed integrally therein;
• a plurality of conductive connectors electrically connecting the first terminals on the substrate to the contacts on the chip;
• and,
• a protective layer of encapsulant covering the contacts, the connectors and the first terminals.