# US 6,291,324 B1 · Method of modeling IC substrate noises utilizing improved doping profile access

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- Number: US 6,291,324 B1
- Document ID: US6291324B1
- Status: Granted
- Kind: B1
- Application number: 09/536,206
- Filed: 2000-03-27
- Granted: 2001-09-18
- Earliest claimed: 1999-03-04
- Assignees: Simplex Solutions, Inc.
- Inventors: Jérôme D. Lescot; Bertrand L. Marchand
- Web page: https://patentgrep.com/patent/US6291324B1

## CPC

- G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for modeling a substrate, which includes obtaining vertically discretized doping profiles in the substrate to facilitate modeling. The method includes employing substrate region names and substrate cross-section names as access keys to permit accessing of the vertically discretized doping profiles. The use of the combination of region names and substrate cross-section names as unique access keys simplifies access to doping profile information for modeling purposes and yields valuable information pertaining to the presence of p-type to n-type material transitions. The information pertaining to transitions may be employed to improve substrate modeling accuracy through the inclusion of junction capacitances with the modeling process.

## Claims

### Claim 1

A method for characterizing an integrated circuit substrate, comprising:
obtaining a substrate doping profile, the substrate doping profile including a net doping level for each one of a plurality of depths within the integrated circuit substrate;
vertically discretizing the substrate doping profile to form a vertically discretized substrate doping profile; and
associating the vertically discretized doping profile with an access key, the access key comprising a region name and a cross-section name.

### Claim 2 (depends on 1)

The method as recited in claim 1, wherein the region name corresponds to a region of the integrated circuit substrate.

### Claim 3 (depends on 2)

The method as recited in claim 2, wherein the region of the integrated circuit substrate is defined by a horizontal area of the integrated circuit substrate.

### Claim 4 (depends on 1)

The method as recited in claim 1, wherein the cross-section name corresponds to a cross-section of the integrated circuit substrate.

### Claim 5 (depends on 4)

The method as recited in claim 4, wherein the cross-section of the integrated circuit substrate is defined by a vertical area of the integrated circuit substrate.

### Claim 6

A method for characterizing an integrated circuit substrate, comprising:
obtaining a substrate doping profile, the substrate doping profile including a net doping level for each one of a plurality of depths within the integrated circuit substrate;
vertically discretizing the substrate doping profile to form a vertically discretized substrate doping profile; and
associating the vertically discretized doping profile with an access key, the access key corresponding to a region of the integrated circuit substrate and a cross-section of the integrated circuit substrate.

### Claim 7 (depends on 6)

The method as recited in claim 6, wherein the region is an area of the integrated circuit substrate in which a number of transitions between p-type material and n-type material within bulk underlying the region is approximately constant within the region.

### Claim 8 (depends on 6)

The method as recited in claim 6, wherein the region is an area of the integrated circuit substrate in which vertical locations of transitions between p-type material and n-type material within bulk underlying the region are approximately constant within the region.

### Claim 9 (depends on 6)

The method as recited in claim 6, wherein the cross-section of the integrated circuit substrate is a default cross-section of the integrated circuit substrate when no specific cross-section is indicated.

### Claim 10 (depends on 6)

The method as recited in claim 6, wherein the region of the integrated circuit substrate is a default region of the integrated circuit substrate when no specific region is indicated.

### Claim 11 (depends on 6)

The method as recited in claim 6, further comprising:
determining from the access key whether to add a junction capacitance.