VDHL/Verilog expertise and gate synthesis automation system
AssigneeLSI Logic Corporation
InventorGuy Dupenloup
Life of this patent
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Abstract
A method of fabricating an integrated circuit chip (IC), said method comprising the steps of defining the IC at the RTL code level, translating said RTL code into a generic netlist description, generating logic synthesis tool scripts based on said generic netlist description, and executing said logic synthesis tool scripts to synthesize the RTL code. The step of generating logic synthesis tool scripts comprises the substeps of identifying hardware elements and structure of the IC design, determining interrelationships between said identified hardware elements and structures, and generating logic synthesis tool scripts to synthesize said identified hardware elements to netlists as a function of said hardware elements and said interrelationships.
Claims12
A method of designing an integrated circuit chip (IC), said method comprising the steps of:
- obtaining a definition of the IC in RTL code;
- translating said RTL code into a generic netlist description;
- generating a logic synthesis tool script based on said generic netlist description;
- executing said logic synthesis tool script to synthesize the RTL code.
A method of generating instructions for a logic synthesis tool to synthesize an integrated circuit chip (IC) design to a gate-level description of the IC design, said method comprising the steps of:
- identifying hardware elements and structure of the IC design;
- determining interrelationships between said identified hardware elements and structure;
- and
- generating a logic synthesis tool script as a function of said hardware elements and said interrelationships.
An apparatus for designing an integrated circuit chip (IC), said apparatus comprising:
- means for obtaining a definition of the IC in RTL code;
- means for translating said RTL code into a generic netlist description;
- means for generating logic synthesis tool scripts based on said generic netlist description;
- means for executing said logic synthesis tool scripts to synthesize the RTL code.
An apparatus for generating instructions for a logic synthesis tool to synthesize an integrated circuit chip (IC) design to a gate-level description of the IC design, said apparatus comprising:
- means for identifying hardware elements and structure of the IC design;
- means for determining interrelationships between said identified hardware elements and structure;
- and
- means for generating a logic synthesis tool script as a function of said hardware elements and said interrelationships.
A computer storage medium having encoded thereon instructions for a computer processor, comprising:
- a computer encoded instruction for obtaining a definition of the IC in RTL code;
- a computer encoded instruction for translating said RTL code into a generic netlist description;
- a computer encoded instruction for generating logic synthesis tool scripts based on said generic netlist description;
- a computer encoded instruction for executing said logic synthesis tool scripts to synthesize the RTL code.
A computer storage medium having instructions thereon for generating instructions for a logic synthesis tool to synthesize an integrated circuit chip (IC) design to a gate-level description of the IC design, said computer storage device comprising:
- a computer encoded instruction for identifying hardware elements and structure of the IC design;
- a computer encoded instruction for determining interrelationships between said identified hardware elements and structure;
- and
- a computer encoded instruction for generating a logic synthesis tool script as a function of said hardware elements and said interrelationships.
Dependencies are inferred from the claim text.