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US 6,289,497 B1Granted
Method and apparatus for N-NARY hardware description language
AssigneeIntrinsity, Inc.
InventorsTimothy S. Leight, Terence M. Potter, James S. Blomgren
Life of this patent
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AssigneeIntrinsity, Inc.
InventorsTimothy S. Leight, Terence M. Potter, James S. Blomgren
Estimating the term…
A syntax statement describing an N-NARY or a CMOS logic circuit having one, and only one, possible configuration of transistors is disclosed. The syntax statement comprises a signal naming convention and one or more gate instantiations using a gate instantiation syntax that includes one or more gate output signal variables described using the signal naming convention, one or more gate operators, and one or more gate expressions using a gate expression syntax that is interpreted to describe the specific transistor configuration of the logic circuit. The signal naming convention includes one or more of the following fields: optional bit and descriptor, signal degree, evaluation, and clock phase. The gate expression syntax further comprises one or more of the following syntaxes: mux select, arithmetic, logical, multiple output, capacitance isolation, or shared node.
A syntax statement that describes the logical and physical characteristics of a logic gate, comprising:
A system that describes the logical and physical characteristics of a logic gate, comprising:
A method of making a syntax statement that describes the logical and physical characteristics of a logic gate, comprising:
A method of using a syntax statement that describes the logical and physical characteristics of a logic gate, comprising:
A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for using a syntax statement that describes the logical and physical characteristics of a logic gate, comprising:
Dependencies are inferred from the claim text.