Circuitry for handling high impedance busses in a scan implementation

An integrated circuit comprising:

• a bus;
• a plurality of bus driver circuits, each bus driver circuit having a driver output connected to the bus to provide an associated driver output signal to the bus, each bus driver circuit further having a high impedance,control node such that an input control signal having a low logic state applied to the control node enables said bus driver circuit to provide an associated driver output signal having either a high logic state or a low logic state, and such that an input control signal having a high logic state applied to said control node causes said bus driver circuit to provide an associated driver output signal having a high impedance state;
• a plurality of scan registers coupled as part of a scan chain such that each of the scan registers in the scan chain responds to a scan test enable signal having the high logic state by initiating a scan-in operation in which test data is sequentially shifted through the scan registers of the scan chain, each one of the scan registers having an output coupled to a scan input of a subsequent scan register in the scan chain and to a data input of a corresponding one of the bus driver circuits;
• and
• for each bus driver circuit, control circuitry that responds to the scan test enable signal having the high logic state by applying an input control signal having the second logic state to the control node of each of said plurality of bus driver circuits, thereby causing each bus driver circuit to provide the high impedance driver output signed to the bus.