Circuit to prevent inadvertent test mode entry
AssigneeMicron Technology, Inc.
InventorJames E. Miller, Jr.
Life of this patent
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Abstract
A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. This circuit is driven by an additional output vector from the circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.
Claims7
A latch regulator for a circuit, comprising;
- a lockout pathway configured to carry a disable signal having a first value and a second value;
- and
- a logic apparatus having:
- a first input node coupled to said lockout pathway,
- a second input node configured to receive a latch prompt signal, and
- an output node configured to couple to said circuit,
- and said logic apparatus configured to recognize a change in said latch prompt signal while said disable signal has said first value and further configured to disregard said change in said latch prompt signal while said disable signal has said second value.
Dependencies are inferred from the claim text.