Fast-scan-flop and integrated circuit device incorporating the same

A scan-flop circuit having a plurality of data input terminals, a select input terminal and a clock input terminal, said scan-flop adapted for use in testing integrity of an integrated circuit's core logic, comprising:

• (a) a multiplexer having a plurality of multiplexer inputs in electrical communication with said data input terminals, a multiplexer select input in electrical communication with said select input terminal, and a multiplexer output, said multiplexer operative in response to a select signal present at said select input terminal to transmit data from one of said data input terminals;
• (b) a synchronous flip-flop having a flip-flop input in electrical communication with said multiplexer output, a clock input in electrical communication with said clock input terminal and a plurality of flip-flop outputs, each of said flip-flop outputs defining a data output terminal for said scan-flop, said flip-flop operative in response to presence of a clocked enable signal at said clock input terminal to exhibit one of a first and second logic state as determined by said data;
• and
• (c) a logic gate having a n output node, said logic gate being electrically connected by an input lead between an NQ output which is one of said flip-flop outputs and its associated said data output terminal to define a scan output terminal for said scan-flop, said input lead having a length of less than about ten (10) microns, said scan output terminal being directly coupled to a serial input terminal of a succeeding scan-flop.

An integrated circuit device, comprising:

• (a) a semiconductor or die;
• (b) a plurality of input pins defined on said semiconductor die;
• (c) a plurality of output pins defined on said semiconductor die;
• and
• (d) a logic core disposed within said semiconductor die, said logic core including a first logic chain electrically connected between paired ones of said input pins and output pins and operative in response to a clocked enable signal present at another of said input pins to receive selected input data and to generate output data at the paired one of said output pins, said logic chain including a first scan-flop, a second scan-flop and a logic array electrically interposed therebetween, each said scan-flop having a data input terminal, a select input terminal, a data output terminal and a scan output terminal, each said scan-flop including a synchronous flip-flop having at least a first flip-flop input adapted to receive selected input data and a plurality of flip-flop outputs, each responsive to the:
• clocked enable signal to exhibit a logic state as determined by the selected input data, a first one of said flip-flop outputs defining the data output terminal of its associated said scan-flop and a second one of said flip-flop outputs defining the scan output terminal of its associated said scan-flop, wherein the data output terminal of said first scan-flop is interconnected through said logic array to the data input terminal of said second scan-flop thereby to define a functional data path between the paired one of said input pins, and output pins, and wherein the scan output terminal of said first scan-flop is directly coupled to the select input terminal of said second scan-flop independently of said logic array thereby to define a logic gate scan path between the paired one of said input pins and output pins, said logic gate scan path being a logic circuit associated with each said flip-flop and electrically coupled between said second flip-flop output and said scan output terminal, wherein said logic circuit is configured to receive an input lead having a length that is less than about ten (10) microns, said integrated circuit device operative in a test mode to transmit selected input data in the form of a test vector to each said scan-flop along said logic gate scan path so that said logic array is bypassed, and further operative in a functional mode to transmit selected input data in the form of functional data through said logic chain along said functional data path for processing by said logic array.

An integrated circuit device, comprising:

• (a) a semiconductor die;
• (b) a plurality input pins defined on said semiconductor die;
• (c) a plurality of output pins defined on said semiconductor die;
• and
• (d) a logic core formed in said semiconductor die and including a plurality of logic chains respectively interconnected for electrical communication between paired ones of said input pins and output pins, each of said logic chains operative to receive selected input data and to generate output data in response thereto, each of said logic chains including:
• (i) a plurality of logic arrays;
• (ii) a plurality of scan-flops each having a data input terminal, a data output terminal, a serial input terminal, and a scan output terminal, said scan output terminal of each of said scan-flops being directly coupled to said serial input terminal of each scan-flop that succeeds each of said scan-flops, each of said scan-flops including a synchronous flip-flop having a flip-flop input adapted to receive the selected input data and a plurality of flip-flop outputs each operative in response to presence of a clocked enable signal to exhibit a logic state as determined by the selected input data, a first one of said flip-flop outputs defining the data output terminal of its associated one of said scan-flops and a second one of said flip-flop outputs defining the scan output terminal of its associated one of said scan-flops, said scan-flops being electrically coupled independently of said logic arrays to define a logic gate scan path between the paired ones of said input pins and output pins, each of said logic gate scan path being a logic circuit associated with each said flip-flop, said logic circuit being configured to receive an input lead having a length that is less than about ten (10) microns, each of said logic gate scan path being electrically connected between said second flip-flop output and said scan output terminal, each of said logic arrays being electrically connected between adjacent ones of said scan-flops thereby to define a functional data path between the paired ones of said input pins and output pins, said integrated circuit device operative in a test mode to transmit selected input data in the form of a test vector to each of said scan-flops along said logic gate scan path so that said logic arrays are bypassed and further operative in a functional mode to transmit selected input data in the form of functional data through said logic chain along said functional data path for processing by said logic arrays.

A method of fabricating an integrated circuit device into a semiconductor die to maximize fault coverage thereof during test mode operation without sacrificing processing speed during functional mode operation, wherein said integrated circuit device includes a plurality of input pins and a plurality of output pins, comprising:

• (a) forming into the semiconductor die a logic core comprising a plurality of logic chains each interconnected for electrical communication between paired ones of said input, pins and said output pins, each of said logic chains comprising a plurality of scan-flops and a plurality of logic arrays and each of said scan-flops including a serial input terminal, a data input terminal, a multiplexer, a flip-flop provided with a flip-flop output, at least one data output terminal electrically coupled directly to said flip-flop output, and a scan output terminal interconnected to said flip-flop output by a logic gate;
• (b) electrically interconnecting each of said logic arrays between the data output terminal of a preceding one of said scan-flops in said logic chain and the data input terminal of a succeeding one of said scan-flops in said logic chain;
• and
• (c) electrically isolating said logic arrays from their associated scan-flops in said logic chain by directly coupling the scan output terminal of each said preceding one of said scan-flops to the serial input terminal of each succeeding one of said scan-flops by a logic gate configured to receive an input lead having a length that is less than ten (10) microns, thereby reducing capacitive loading effects on the data output terminal of each said flip-flop during testing mode operation and functional mode operation of the integrated circuit device.