Method and apparatus for testing the timing of integrated circuits
AssigneeMicron Technology, Inc.
InventorTimothy B. Cowles
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes a first external pin and an input buffer connected to the first external pin. The input buffer includes an output terminal and a first test mode input terminal adapted to disable the output terminal in response to a first test mode signal. A method for testing an integrated circuit, the integrated circuit including a first external pin and an input buffer, includes providing a first external input signal to the first external pin at a first specified time, and disabling the input buffer at a second specified time after the first specified time.
Claims39
An integrated circuit, comprising:
- a first external pin;
- an input buffer connected to the first external pin, wherein the input buffer includes an output terminal and a first test mode input terminal adapted to disable the output terminal in response to assertion of a first test mode signal
- wherein said first test mode signal is asserted in a predetermined timed relationship with assertion of an external input signal on said external pin.
A method for testing an integrated circuit, the integrated circuit including a first external pin coupled to an input buffer, the method comprising:
- providing a first external input signal to the first external pin at a first specified time;
- disabling the input buffer at a second specified time after the first specified time such that an output signal from said input buffer is controlled for the purpose of testing timing specifications of said integrated circuit.
An integrated circuit, comprising:
- a first external pin;
- and
- an input buffer connected to the first external pin, wherein the input buffer includes an output terminal and first and second test mode input terminals, the first and second test mode input terminals adapted to disable the output terminal in response to respective first and second test mode signals;
- a second external pin adapted to receive an external clock signal;
- and
- a delay element connected to the second external pin and adapted to provide a delayed clock signal, the delay element being coupled to the second test mode input terminal.
Dependencies are inferred from the claim text.