Storage device array architecture with solid-state redundancy unit

A storage subsystem comprising:

• a storage controller coupling a central processing unit to a plurality of data storage units in a redundant array, at least one of said data storage units having an access time that is different from at least another of said storage units, said storage controller operative for placing primarily accessed data on a fastest one of said failure independent data storage units.

A fault tolerant storage subsystem comprising:

• a plurality of failure independent data storage units for storing a plurality of data blocks and at least one associated redundancy block, at least one of said plurality of failure independent data storage units comprising a solid state data storage unit having a Read and Write cycle time substantially lesser than a Read and Write cycle time of each other of said failure independent data storage units and wherein selected ones of said plurality of said data blocks and said at least one associated redundancy block which are most frequently accessed during a data modification operation are stored on said at least one solid state data storage unit to decrease Read and Write operation times of said frequently accessed data to that of said solid state data storage unit.

A computer comprising:

• a central processing unit;
• a storage subsystem controller coupled to said central processing unit;
• a plurality of first tier failure independent data storage units coupled to said controller in a redundant array, at least one of said plurality of failure independent data storage units having a Read and Write cycle time substantially differing from at least one other of said failure independent data storage units.

A fault tolerant storage subsystem comprising:

• a plurality of failure independent data storage units coupled to a storage controller in a redundant array, said plurality of failure independent data storage units comprising at least first and second data storage units having substantially differing Read and Write cycle times.