Data monitor circuit
AssigneeWilmington Trust Company
InventorToshiyuki Tanaka
Life of this patent
Estimating the term…
Abstract
Address information that is desired to be monitored of a data storage memory is stored in a data memory address buffer 110, and while a program is being executed the stored address information and address information transferred to a bus are compared. If there is coincidence between the stored address information and the address information transferred to the bus, data that has been transferred to the bus (data that has been read or written based on coincident address information) can be reliably output to the outside. As a result, it is possible to reliably carry out defect analysis for a data storage memory while a program is being executed.
Claims10
A data monitoring circuit for monitoring data transferred on a bus when at least reading of data from a first memory circuit is carried out via the bus according to a specified program, comprising:
- a first address storage circuit for storing address information of said memory circuit to be monitored;
- a first comparison circuit for receiving address information designated by said specified program via the bus and detecting coincidence with address information stored in said first address storage circuit;
- a first data storage circuit for storing data transferred on the bus;
- a first gate circuit for transferring data being transferred to the bus to said first data storage circuit in response to a first permission signal;
- and
- a control circuit for outputting said first permission signal according to a detection result of said first comparison circuit.
Dependencies are inferred from the claim text.