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US 6,289,469 B1Granted
Semiconductor integrated circuit having a plurality of processing circuits respectively executing necessary processes and a plurality of data holding circuits corresponding to the processing circuits
AssigneeOki Electric Industry Co., Ltd.
InventorsYoshio Sakata, Yoshio Tokuno, Junichi Tamura, Yumiko Uehara
Life of this patent
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Abstract
A control signal generating circuit for generating control signals, based on a first clock signal, a second clock signal and a mode setting signal, and a plurality of scanpath circuits. Operation of each of the scanpath circuits is controlled according to the generated control signals. The control signal generating circuit and scanpath circuits are provided in a semiconductor integrated circuit having reduced size.
Claims18
A semiconductor integrated circuit comprising:
- a plurality of processing circuits that respectively execute necessary processes;
- a plurality of data holding circuits respectively provided so as to correspond to said plurality of processing circuits, said plurality of data holding circuits being respectively activated independently in a first operating mode and activated as shift registers by being cascade-connected in a second operating mode;
- each of said data holding circuits including
- a first data input terminal supplied with first data output from a corresponding processing circuit,
- a second data input terminal supplied with second data output from another data holding circuit,
- a first output terminal,
- a clock input terminal supplied with a clock signal,
- a gate circuit electrically connected with said first and second data input terminals, said gate circuit outputs the first data as third data based on a first control signal and outputs the second data as the third data based on a second control signal, and
- a latch circuit electrically connected with said gate circuit, said first output terminal, and said clock input terminal, said latch circuit latches the third data in accordance with the clock signal and outputs the latched data from said first output terminal;
- and
- a control signal generating circuit electrically connected with said data holding circuits, said control signal generating circuit having input terminals respectively receiving a mode signal indicative of the first operating mode or the second operating mode, a first clock signal and a second clock signal, said control signal generating circuit generates and outputs the first control signal, the second control signal, and the clock signal based on states of the signals input thereto.
8 more elements
A semiconductor integrated circuit comprising:
- a plurality of processing circuits that respectively execute corresponding processes;
- a plurality of data holding circuits that are respectively coupled to corresponding pairs of said plurality of processing circuits, said plurality of data holding circuits each being operable in a first mode to pass processed data between the corresponding pairs of said plurality of processing circuits and in a second mode as shift registers cascade-connected to pass test data through said plurality of data holding circuits;
- a scanpath input terminal that receives and provides the test data directly to a test input terminal of a first data holding circuit of said plurality of data holding circuits;
- and
- a control signal generating circuit that receives first and second clock signals and a mode signal, and that generates a system clock signal that directly controls timing of said plurality of data holding circuits and that generates control signals that control said plurality of data holding circuits to selectively latch the corresponding test data or the corresponding processed data at each of said data holding circuits.
2 more elements
Dependencies are inferred from the claim text.