Circuit and method for initiating exception routines using implicit exception checking

In a microprocessor configured to execute instructions, a method of initiating an exception routine in response to a memory access exception caused by a first instruction for loading one of a plurality of architectured registers with data from memory, the method comprising:

• generating exception information in response to the memory access exception caused by the first instruction;
• storing the exception information within one of a plurality of exception registers, wherein each of said exception registers corresponds to at least one of the plurality of architectured registers;
• receiving and decoding a second instruction for operating on data stored in the architectured register;
• checking the contents of an exception register corresponding to the architectured register in response to receiving and decoding the second instruction;
• and
• initiating the exception routine if the exception register contains exception information, or executing the second instruction to operate on data contained in the architectured register if the exception register does not contain exception information.

A microprocessor for executing instructions including speculative load instructions, which cause memory access exceptions, the microprocessor comprising:

• a plurality of first registers for storing data received from memory in response to executing speculative load instructions;
• a plurality of second registers for storing exception information to be used by an exception handling routine;
• an exception information generator coupled to the plurality of second registers, wherein the exception information generator is configured to generate exception information in response to memory access exceptions caused by speculative load instructions;
• an execution unit coupled to the plurality of first and second registers, wherein the execution unit is configured to execute instructions including instructions which operate on data stored in the plurality of first registers, wherein the execution unit is configured to receive data stored in a second register in response to receiving an instruction for operating on data contained in a first register, wherein the execution unit executes the instruction to operate on data contained in the first register if the received data is not exception information.

In a microprocessor configured to execute instructions, a method of initiating an exception routine in response to an exception caused by a first instruction for loading one of a plurality of first registers with data, the method comprising:

• generating exception information in response to the exception caused by the first instruction;
• storing the exception information within one of a plurality of second registers, wherein each of the second registers corresponds to at least one of the plurality of first registers;
• receiving and decoding a second instruction for operating on data stored in a first register;
• checking the contents of a second register corresponding to the first register in response to receiving and decoding the second instruction, and;
• initiating the exception routine if the second register contains exception information, or executing the instruction to operate on data contained in the first register if the second register does not contain exception information.

A microprocessor for executing instructions including speculative load instructions which cause memory access exceptions, the microprocessor comprising:

• a plurality of first registers for storing data received from memory in response to executing speculative load instructions;
• a plurality of second registers for storing exception information to be used by an exception handling routine;
• an exception information generator coupled to the plurality of second registers, wherein the exception information generator is configured to generate exception information in response to memory access exceptions caused by speculative load instructions;
• an execution unit coupled to the plurality of first and second registers, wherein the execution unit is configured to execute instructions including instructions which operate on data stored in the plurality of first registers, wherein the execution unit is configured to receive data stored in a second register in response to receiving an instruction for operating on data contained in a first register, wherein the execution unit executes the instruction if the received data is not exception information;
• wherein the execution unit is configured to execute the exception routine using exception information stored in the second register;
• wherein the plurality of first and second registers are equal in number;
• wherein exception information includes an instruction address of a speculative load instruction.