US 6,289,442 B1 · Circuit and method for tagging and invalidating speculatively executed instructions

Abstract

A method and circuit is disclosed for tagging and invalidating speculatively executed instructions. The method includes fetching a first plurality of instructions which includes a conditional branch instruction which identifies a target address if the branch is taken. The conditional branch instruction is detected and in response thereto first and second instruction tags are generated. At least a first instruction is tagged with the first instruction tag wherein the first instruction is included in the first plurality of instructions and wherein the first instruction sequentially follows the first conditional branch instruction in program order. Thereafter, a second plurality of instructions are fetched wherein the second plurality of instructions corresponds to the target address of the conditional branch instruction. At least one of these second plurality of instructions is tagged with the second instruction tag. Thereafter, the conditional branch instruction is executed and resolved. A branch status operand is generated in response to executing the conditional branch instruction wherein the branch status operand indicates whether the conditional branch instruction is resolved as taken or not taken. The generated branch status operand is compared against the first and second instruction tags. In response to comparing the branch status operand, one of the first and second instructions is invalidated indicating that it was within the wrong program path of execution.

Claims26

Dependent claims

A method of tagging speculatively issued instructions within a microprocessor comprising:

fetching a plurality of consecutive instructions;
detecting a conditional branch instruction within said plurality of consecutive instructions;
tagging a first instruction with a first tag corresponding to said conditional branch instruction in response to detecting the conditional branch instruction, wherein said first instruction corresponds to a target address of said conditional branch instruction, and wherein the first tag indicates that the first instruction is in correct program order if the conditional branch instruction is taken;
and
tagging remaining instructions within said plurality of consecutive instructions subsequent to said conditional branch instruction with a second tag corresponding to said conditional branch instruction in response to detecting the conditional branch instruction, wherein the second tag indicates that said remaining instructions are in correct program order if the conditional branch instruction is not taken.

2 more elements

A microprocessor comprising:

a fetch unit configured to fetch a plurality of consecutive instructions;
an instruction decoder configured to receive and decode said plurality of consecutive instructions, wherein said plurality of consecutive instructions includes a conditional branch instruction, wherein said conditional branch instruction includes a branch target address identifying a branch target instruction;
a plurality of functional units configured to execute decoded instructions received from the instruction decoder;
an instruction tag circuit coupled to said instruction decoder and configured to generate first and second instruction tags corresponding to said conditional branch instruction, wherein said instruction tag circuit is configured to tag remaining instructions within said plurality of consecutive instructions following said conditional branch instruction in sequence with said first instruction tag, and wherein said instruction tag circuit is configured to tag said branch target instruction with said second instruction tag.

1 more element

Dependencies are inferred from the claim text.

Circuit and method for tagging and invalidating speculatively executed instructions

Life of this patent

Circuit and method for tagging and invalidating speculatively executed instructions

Life of this patent

Abstract

Claims26