US 6,289,438 B1 · Microprocessor cache redundancy scheme using store buffer

Abstract

A method and apparatus for bypassing defective cache memory locations on-board a microprocessor integrated circuit chip, which includes a processor, a cache memory, a store buffer, a tag RAM, and a comparator. The cache memory has a plurality of valid cache memory locations and at least one defective cache memory location. The store buffer has buffer entries and redundancy entries for storing data sent by the processor for storage in the cache memory. The tag RAM has buffer tag entries for storing addresses of data stored in the buffer entries and redundancy tag entries that store addresses of defective cache memory locations in the cache memory. The comparator compares addresses of data sent by the processor for cache memory storage with addresses stored in the redundancy tag entries. For each data sent by the processor for cache memory storage, if the data address matches an address stored in one of the redundancy tag entries, then the store buffer stores that data in the corresponding redundancy entry, otherwise the store buffer stores that data in one of the buffer entries. The store buffer sends data stored in the buffer entries to the cache memory for storage in the valid cache memory locations, but the data stored in the redundancy entries (corresponding to defective cache memory locations) is retained in the store buffer. Therefore, when the processor wants to retrieve data with an address corresponding to the defective cache memory location, the requested data is supplied by the corresponding redundancy entry of the store buffer.

Claims20

Dependent claims

A microprocessor integrated circuit chip, comprising:

a processor;
a cache memory having a plurality of valid cache memory locations and at least one defective cache memory location;
a store buffer having buffer entries and redundancy entries for storing data sent by the processor for storage in the cache memory;
a tag RAM having buffer tag entries for storing addresses of data stored in the buffer entries and redundancy tag entries for storing addresses of defective cache memory locations in the cache memory;
and
a comparator for comparing addresses of data sent by the processor for cache memory storage with addresses stored in the redundancy tag entries;
wherein, for each data sent by the processor for cache memory storage, if the data address matches an address stored in one of the redundancy tag entries, then the store buffer stores that data in the corresponding redundancy entry, otherwise the store buffer stores that data in one of the buffer entries;
and
wherein the store buffer sends data stored in the buffer entries to the cache memory for storage in the valid cache memory locations.

6 more elements

A method of bypassing defective cache memory locations in a cache memory area of a microprocessor integrated circuit chip that also includes a processor, a store buffer with buffer entries and redundancy entries for storing data, and a tag RAM with buffer tag entries and redundancy tag entries for storing data addresses, the cache memory having valid and defective cache memory locations, the method comprising the steps of:

storing non-volatile addresses of defective cache memory locations in the redundancy tag entries;
comparing addresses of data sent by the processor for cache memory storage with addresses stored in the redundancy tag entries;
storing the data sent by the processor for cache memory storage in the store buffer, wherein the data having addresses matching addresses stored in the redundancy tag entries are stored in the redundancy entries, and the data having addresses not matching addresses stored in the redundancy tag entries are stored in the buffer entries;
and
writing the data stored in the buffer entries to the valid cache memory locations.

2 more elements

A microprocessor integrated circuit chip, comprising:

processor means for writing data to cache memory storage and for retrieving data from cache memory storage;
cache memory means for storing data in cache memory locations;
store buffer means having:
buffer entries for receiving and storing data sent by the processor for storage in the cache memory,
means for sending data stored in the buffer entries to the cache memory for storage in the valid cache memory locations, and
redundancy entries for receiving and storing data sent by the processor for storage in the cache memory, wherein the data stored in the redundancy entries is not sent to the cache memory means for storage therein;
tag RAM means for storing data addresses, the tag RAM means having buffer tag entries for storing addresses of data stored in the buffer entries and redundancy tag entries for storing addresses of defective cache memory locations in the cache memory;
and
comparator means for comparing addresses of data sent by the processor for cache memory storage with addresses stored in the redundancy tag entries;
and
means for storing each data sent by the processor for cache memory storage in the store buffer means for storage either in one of the redundancy tag entries or in one of the buffer entries.

8 more elements

Dependencies are inferred from the claim text.

Microprocessor cache redundancy scheme using store buffer

Life of this patent

Microprocessor cache redundancy scheme using store buffer

Life of this patent

Abstract

Claims20