Superscalar RISC instruction scheduling

A computer system, comprising:

• a memory unit for storing program instructions;
• a bus coupled to said memory unit for retrieving said program instructions;
• and
• a processor coupled to said bus, wherein said processor comprises a register renaming system, comprising:
• a temporary buffer comprising a plurality of storage locations for storing execution results, wherein an execution result for an instruction in an instruction window is stored at one of said plurality of storage locations, said one of said plurality of storage locations being assigned to said instruction in said instruction window;
• and
• tag assignment logic that receives data dependency results from a data dependency checker and outputs a temporary buffer storage location address in place of a register address for an operand of a first instruction if said first instruction is dependent on a previous one of said plurality of instructions in said instruction window for said operand, wherein said temporary buffer storage location address is an address of said operand in one of said plurality of storage locations.

A register renaming method, comprising the steps of:

• (1) storing, in a temporary buffer, out-of-order execution results in storage locations assigned to instructions in an instruction window;
• (2) generating at least one tag to specify an address in said temporary buffer at which said out-of-order execution results are temporarily stored;
• and
• (3) outputting one of said at least one tag comprising an address in place of a register address for an operand of a first instruction if a data dependency result indicates that said first instruction is dependent on a previous instruction in said instruction window, wherein said tag comprises an address of said operand in said temporary buffer.