Method and apparatus for accessing more than 4 Gigabytes of physical memory with 4-byte table entries

A method for accessing paged memory comprising:

• decoding a linear address;
• accessing a page directory table entry that provides a base address in response to decoding the linear address;
• if the page directory table entry corresponds to a first page of a first predetermined size, then
• accessing a page table having a page table base address corresponding to the base address, wherein the page table has an entry that inherits permissions from the page directory table entry and provides a first page base address of the first page, and
• accessing a physical address in the first page corresponding to the linear address;
• if the page directory table entry corresponds to a second page of a second predetermined size, then
• accessing a second physical address in the second page, wherein the second page has a second page base address corresponding to the base address in the page directory entry, and further wherein the second physical address corresponds to the linear address.

A system comprising:

• a bus;
• a memory coupled to the bus;
• and
• a processor coupled to the bus, wherein the processor accesses the memory via a paging system having two page sizes, further wherein pages of one of the two page sizes are accessed by a page directory entry and a page table entry where the page table entry inherits permissions from the page directory entry.