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US 6,289,429 B1Granted
Accessing multiple memories using address conversion among multiple addresses
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorMinoru Okamoto
Life of this patent
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Abstract
A memory device including a first memory and a second memory. A first processor generates a first address for defining a location to be accessed in the first memory and a second address for defining a location to be accessed in the second memory. A second processor generates a third address. A memory control section controls access to the first memory and access to the second memory. The memory control section includes an address conversion section for converting the third address so as to represent either one of the first address and the second address.
Claims22
A memory device, comprising:
- a first single-port memory;
- a second single-port memory;
- a first processor for generating a first address for defining a location to be accessed in the first single-port memory, a first control signal for activating the first single-port memory, a second address for defining a location to be accessed in the second single-port memory, and a second control signal for activating the second single-port memory;
- a second processor for generating a third address not compatible with the first and second single-port memories;
- and
- a memory control section for controlling access to the first single-port memory and access to the second single-port memory, the memory control section including an address conversion section for converting the third address so as to represent either one of the first address and the second address, and for generating either one of the first control signal and the second control signal based on at least a portion of the third address.
3 more elements
A memory device, comprising;
- a first single-port memory;
- a second single-port memory;
- a processor for generating a first address for defining a location to be accessed in the first single-port memory, a first control signal for activating the first single-port memory, a second address for defining a location to be accessed in the second single-port memory, a second control signal for activating the second single-port memory, and a third address not compatible with the first and second single-port memories;
- and
- a memory control section for controlling access to the first single-port memory and access to the second single-port memory, the memory control section including an address conversion section for converting the third address so as to represent either one of the first address and the second address, and for generating either one of the first control signal and the second control signal based on at least a portion of the third address.
2 more elements
A method for accessing a first single-port memory and a second single-port memory in a memory device, the method comprising the steps of:
- generating a first address for defining a location to be accessed in the first single-port memory and a second address for defining a location to be accessed in the second single-port memory;
- generating a third address not compatible with the first and second single-port memories;
- and
- controlling access to the first single-port memory and access to the second single-port memory with a first control signal and a second control signal,
- wherein the step of controlling includes the step of converting the third address so as to represent either one of the first address and the second address, and for generating either one of the first control signal and the second control signal.
2 more elements
A memory device, comprising:
- a first memory having an address port which receives a first address in order to access the first memory;
- a second memory having an address port which receives a second address in order to access the second memory;
- a first processor and a second processor, the first processor being configured to generate the first address for defining a location to be accessed in the first memory and the second address for defining a location to be accessed in the second memory, and the second processor being configured to generate a third address which in one case represents a location to be accessed in the first memory and in another case represents a location to be accessed in the second memory;
- and
- a memory control section for controlling access to the first memory and access to the second memory, the memory control section including an address conversion section for converting the third address received from the second processor according to a predefined criteria so as to generate the first address in the one case and the second address in the another case.
2 more elements
A memory device, comprising:
- a first single-port memory;
- a second single-port memory;
- a first processor for generating a first address for defining a location to be accessed in the first single-port memory, a first control signal for activating the first single-port memory, a second address for defining a location to be accessed in the second single-port memory, and a second control signal for activating the second single-port memory;
- a second processor for generating a third address not compatible with the first and second single-port memories;
- a memory control section for controlling access to the first single-port memory and access to the second single-port memory, the memory control section including an address conversion section for converting the third address so as to represent either one of the first address and the second address, and for generating either one of the first control signal and the second control signal based on at least a portion of the third address;
- and
- an arbitration circuit for arbitrating an access request from the first processor and the second processor.
4 more elements
A memory device, comprising:
- a first single-port memory;
- a second single-port memory;
- a first processor which generates a first address that defines a location to be accessed in the first single-port memory, a first control signal for activating the first single-port memory, a second address that defines a location to be accessed in the second single-port memory, and a second control signal for activating the second single-port memory;
- a second processor which generates a third address not compatible with the first single-port memory and the second single-port memory;
- and
- a memory control section which allows the first processor simultaneous access to both the first single-port memory and the second single-port memory, the memory control section including an address conversion section capable of converting the third address so as to represent both the first and second memories whereby the third address may be converted to represent either one of the first address and the second address, and for generating either one of a first control signal and a second control signal.
3 more elements
Dependencies are inferred from the claim text.