US 6,289,428 B1 · Superscaler processor and method for efficiently recovering from misaligned data addresses

Abstract

A superscalar processor and method are disclosed for efficiently recovering from misaligned data addresses. The processor includes a memory device partitioned into a plurality of addressable memory units. Each of the plurality of addressable memory units has a width of a first plurality of bytes. A determination is made regarding whether a data address included within a memory access instruction is misaligned. The data address is misaligned if it includes a first data segment located in a first addressable memory unit and a second data segment located in a second addressable memory unit where the first and second data segments are separated by an addressable memory unit boundary. In response to a determination that the data address is misaligned, a first internal instruction is executed which accesses the first memory unit and obtains the first data segment. A second internal instruction is executed which accesses the second memory unit and obtains the second data segment. The first and second data segments are merged together. All of the instructions executed by the processor are constrained by the memory boundary and do not access memory across the memory boundary.

Claims14

Dependent claims

A method in a superscalar processor for efficiently recovering from misaligned data addresses, said processor including a memory device partitioned into a plurality of addressable memory units, each of said plurality of addressable memory units having a width of a first plurality of bytes, said method comprising the steps of:

determining whether a data address included within a memory access instruction is misaligned, said data address being misaligned when said data address includes a first data segment located in a first addressable memory unit and a second data segment located in a second addressable memory unit, said first and second data segments being separated by an addressable memory unit boundary;
in response to a determination that said data address is misaligned, replacing said memory access instruction with a first, a second, and a third internal instruction;
executing said first internal instruction which accesses said first memory unit and obtains only said first data segment;
executing said second internal instruction which accesses said second memory unit and obtains only said second data segment;
and
executing said third instruction, said third instruction merging said first and second data segments together, so that in response to said memory access instruction having the misaligned data address, the processor executes the plurality of internal instructions having aligned data addresses.

3 more elements

A superscalar processor for efficiently recovering from misaligned data addresses, said processor including a memory device partitioned into a plurality of addressable memory units, each of said plurality of addressable memory units having a width of a first plurality of bytes, comprising:

means for determining whether a data address included within a memory access instruction is misaligned, said data address being misaligned when said data address includes a first data segment located in a first addressable memory unit and a second data segment located in a second addressable memory unit, said first and second data segments being separated by an addressable memory unit boundary;
means for replacing said memory access instruction with a first, a second, and a third internal instructions, in response to a determination that said data address is misaligned;
means for executing said first internal instruction which accesses said first memory unit and obtains only said first data segment;
means for executing said second internal instruction which accesses said second memory unit and obtains only said second data segment;
and
means for executing said third instruction, said third instruction merging said first and second data segments together, so that in response to said memory access instruction having the misaligned data address, the processor executes the plurality of internal instructions having aligned data addresses.

3 more elements

Dependencies are inferred from the claim text.

Superscaler processor and method for efficiently recovering from misaligned data addresses

Life of this patent

Superscaler processor and method for efficiently recovering from misaligned data addresses

Life of this patent

Abstract

Claims14