Controlling a read address or a write address based on the quantity of data read from or written into a memory
AssigneeCanon Kabushiki Kaisha
InventorYasuyuki Tanaka
Life of this patent
Estimating the term…
Abstract
Even if the timing of reading or writing the data of a predetermined quantity deviates, missing data can be minimized. The data quantity read from memory which stores the predetermined numbers of the fixed-length data is detected, the data quantity detected is compared with a predetermined value, and a reading address of the memory is controlled in accordance with the comparison result. Also, the data quantity written into the memory which stores the predetermined numbers of the fixed-length data is detected, the data quantity detected is compared with a predetermined value, and a writing address of the memory is controlled in accordance with the comparison result.
Claims39
A device for controlling a memory to write fixed-length data packets, comprising:
- counting means for counting a quantity of data for a first fixed-length data packet being written into the memory;
- comparing means for comparing the counted quantity of the data with a first predetermined value;
- and
- addressing controlling means for revising a value of a write address for writing a second fixed-length data packet into the memory, writing of the second fixed-length data packet following that of the first fixed-length data packet, the value of the write address being revised to a second predetermined value based on a result of the comparing means.
A receiver, comprising:
- receiving means for receiving fixed-length data packets and writing the fixed-length data packets into a memory;
- counting means for counting a quantity of data for a first fixed-length data packet being written into the memory;
- comparing means for comparing the counted quantity of the data with a first predetermined value;
- and
- address controlling means for revising a value of a write address for writing a second fixed-length data packet into the memory, writing of the second fixed-length data packet following that of the first fixed-length data packet, the value of the write address being revised to a second predetermined value based on a result of the comparing means.
A transmitter for transmitting fixed-length data packets, comprising:
- counting means for counting a quantity of data for a first fixed-length data packet being read from a memory;
- comparing means for comparing the counted quantity of the data with a first predetermined value;
- address controlling means for revising a value of a read address for reading a second fixed-length data packet from the memory, reading of the second fixed-length data packet following that of the first fixed-length data packet, the value of the read address being revised to a second predetermined value based on a result of the comparing means;
- and
- transmitting means for transmitting the fixed-length data packets read from the memory.
A method of controlling a memory to write fixed-length data packets, comprising:
- a counting step of counting a quantity of data for a first fixed-length data packet being written into the memory;
- a comparing step of comparing the counted quantity of the data with a first predetermined value;
- and
- an address controlling step of revising a value of a write address for writing a second fixed-length data packet into the memory, writing of the second fixed-length data packet following that of the first fixed-length data packet, to a second predetermined value based on a result of the comparing step.
A method of controlling a receiver, comprising:
- a receiving step of receiving packets corresponding to fixed-length data packets and writing the fixed-length data packets into a memory;
- a counting step of counting a quantity of data for a first fixed-length data packet being written into the memory;
- a comparing step of comparing the counted quantity of the data with a first predetermined value;
- and
- an address controlling step of revising a value of a write address for writing a second fixed-length data packet into the memory, writing of the second fixed-length data packet following that of the first fixed-length data packet, the value of the write address being revised to a second predetermined value based on a result of the comparing step.
A method of controlling a transmitter which transmits fixed-length data packets, comprising:
- a counting step of counting a quantity of data for a first fixed-length data packet being read from a memory;
- a comparing step of comparing the counted quantity of the data with a first predetermined value;
- an address controlling step of revising a value of a read address for reading a second fixed-length data packet from the memory, reading of the second fixed-length data packet following that of the first fixed-length data packet, the value of the read address being revised to a second predetermined value based on the results of the comparing step;
- and
- a transmitting step of transmitting the fixed-length data packets read from memory.
A device for controlling a memory to read fixed-length data packets, comprising:
- counting means for counting a quantity of data for a first fixed-length data packet being read from the memory;
- comparing means for comparing the counted quantity of the data with a first predetermined value;
- and
- address controlling means for revising a value of a read address for reading a second fixed-length data packet from the memory, reading of the second fixed-length data packet following that of the first fixed-length data packet, the value of the read address being revised to a second predetermined value based on a result of the comparing means.
A method of controlling a memory to read fixed-length data packets, comprising:
- a counting step of counting a quantity of data for a first fixed-length data packet being read from the memory;
- a comparing step of comparing the counted quantity of data with a first predetermined value;
- and
- an address controlling step of revising a value of a read address for reading a second fixed-length data packet from the memory, reading of the second fixed-length data packet following that of the first fixed-length data packet, the value of the read address being revised to a second predetermined value based on a result of the comparing step.
Dependencies are inferred from the claim text.