System and method for increasing the snoop bandwidth to cache tags in a multiport cache memory subsystem

A cache memory subsystem comprising:

• a cache controller;
• and
• a cache memory coupled to said cache controller for storing a plurality of cache lines, wherein said cache memory includes a plurality of memory sections, wherein each of said memory sections is separately addressable through separate address lines coupled to said cache controller, and wherein each memory section of said cache memory is configured to store a portion of each of said plurality of cache lines;
• wherein said cache controller is configured to control accesses to said cache memory such that a first set of address tags corresponding to a first subset of said plurality of cache lines is stored in a first of said plurality of memory sections and such that a second set of address tags corresponding to a second subset of said plurality of cache lines is stored in a second of said plurality of memory sections;
• wherein each of said plurality of cache lines includes a tag field to store a corresponding address tag and a data field to store corresponding data, and wherein said tag field further stores state information indicative of a coherency state of said corresponding data.

A computer system comprising:

• a processor;
• and
• a cache memory subsystem coupled to said processor, wherein said cache memory subsystem includes:
• a cache controller;
• and
• a cache memory coupled to said cache controller for storing a plurality of cache lines, wherein said cache memory includes a plurality of memory sections, wherein each of said memory sections is separately addressable through separate address lines coupled to said cache controller, and wherein each memory section of said cache memory is configured to store a portion of each of said plurality of cache lines;
• wherein said cache controller is configured to control accesses to said cache memory such that a first set of address tags corresponding to a first subset of said plurality of cache lines is stored in a first of said plurality of memory sections and such that a second set of address tags corresponding to a second subset of said plurality of cache lines is stored in a second of said plurality of memory sections;
• wherein each of said plurality of cache lines includes a tag field to store a corresponding address tag and a data field to store corresponding data, and wherein said tag field further stores state information indicative of a coherency state of said corresponding data.