Address pipelined stack caching method

Abstract

The present invention uses a stack management unit including a stack cache to accelerate data retrieval from a stack and data storage into the stack. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit maintains a cached stack portion, typically a top portion of the stack in the stack cache. The stack cache includes a stack cache memory circuit, one or more read ports, and one or more write ports. The stack management unit also includes an address pipeline to transfer multiple data words by the spill control unit and the fill control unit to improve the throughput of spill and fill operations. When new data words are written to the top memory location of the stack, the optop pointer is incremented. If data words are read off the stack the optop pointer is decremented. During normal operations the dribble manager unit detects spill conditions and fill conditions. If a spill condition occurs, the dribble manager unit spills a plurality of data words from the stack cache to the stack. If a fill condition occurs, the dribble manager unit fills a plurality of data words from the stack to the stack cache.

Dependencies are inferred from the claim text.