Cached synchronous DRAM architecture having a mode register programmable cache policy

A method of implementing a programmable caching policy on a cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture, said method comprising the steps of:

• providing a synchronous dynamic random access memory (SDRAM) bank including a row decoder coupled to a memory bank array for selecting a row of data in the memory bank array, sense amplifiers coupled to the memory bank array via bit lines for latching the row of data selected by the row decoder, and a synchronous column means for selecting a desired column of the row of data;
• providing a randomly addressable row register for storing a row of data latched by the sense amplifiers;
• providing a select logic gating means, disposed between the sense amplifiers and the row registers, for selectively gating the row of data present on the bit lines to the row register in accordance to particular synchronous memory operations of the cached SDRAM being performed, wherein data to be input into the cached SDRAM during a Write operation is received by the sense amplifiers and written into the memory bank array and wherein data to be output from the cached SDRAM during a Read operation is read out only from the row register, the row of data contained in the row register first having been read from the memory bank array to the sense amplifiers and then selectively gated to the row register in accordance with the particular synchronous memory operations;
• and
• programming of the cached SDRAM to operate in a Write Transfer mode corresponding to a Normal Operation mode of a standard SDRAM during a Write cycle, and to operate in a No Write Transfer mode according to an alternate operation mode during a Write cycle, thereby operating under a first and a second caching policy, respectively.

A cached synchronous dynamic random access memory device comprising:

• external clock means coupled to said memory device;
• first and second synchronous dynamic random access memory banks;
• a first row decoder coupled to the first memory bank array for selecting a row of data in the first memory bank array;
• a first set of sense amplifiers coupled to the first memory bank array for latching the row of data selected by the first row decoder;
• a first row register coupled to the first set of sense amplifiers for storing a row of data latched by the first set of sense amplifiers;
• a first column decoder coupled to the first row register for selecting a desired column of the row of data selected by the first row decoder and stored in the first row register;
• a first column write select logic means, disposed between said first set of sense amplifiers and the first row register for gating a row of data from the first set of sense amplifiers to the firs row register;
• first data latches coupled between data I/O buffers an the first row register for latching data output, from the first row register to the I/O buffers and from the I/O buffers to the first set of sense amplifiers wherein data to be input into the cached synchronous dynamic random access memory device during a Write operation is received by the first sense amplifiers and written into the first memory bank array and data to be output from the cached synchronous dynamic random access memory device during a Read operation is read out only from the first row register, the row of data contained in the first row register having been read from the first memory bank array to the first sense amplifiers and then selectively gated to the first row register in accordance with a selected synchronous memory operation;
• a second row decoder coupled to the second memory bank array for selecting a row of data in the second memory bank array;
• a second set of sense amplifiers coupled to the second memory bank array for latching the row of data selected by the second row decoder;
• a second row register coupled to the second set of sense amplifiers for storing a row of data latched by the second set of sense amplifiers;
• a second column decoder coupled to the second row register for selecting a desired column of the row of data selected by the second row decoder and stored by the second row register;
• a second column write select logic means, disposed between said second set of sense amplifiers and the second row register for gating a row of data from the second set of sense amplifiers to the second row register;
• second data latches coupled between the data I/O buffers and the second row register for latching data output from the second row register to the data I/O buffers and from the data I/O buffers to the second set of sense amplifiers wherein data to be input into the cached synchronous dynamic random access memory device during a Write operation is received by the second set of sense amplifiers and written into the second memory bank array and data to be output from the cached synchronous dynamic random access memory device during a Read operation is read out only from the second row register, the row of data contained in the second row register having been read from the second memory bank array to the second sense amplifiers and then selectively gated to the second row register in accordance with a selected synchronous memory operation;
• the data output from the cached synchronous dynamic random access memory device, and from the first and second row registers, being synchronized with the output signals from said external clock;
• and
• control means for enabling concurrent memory operations to occur on said first and second row registers and the respective first and second memory bank arrays coupled thereto.