Layout synopsizing process for efficient layout parasitic extraction and circuit simulation in post-layout verification

A process of generating a synoptic layout database for efficient layout parasitic extraction and circuit simulation in post-layout verification of an integrated circuit (IC) design for a system having a plurality of repetitive sub-circuits, the process comprising the steps of:

• receiving an input layout database including a plurality of layout cells geometrically representing the IC design, each of said cells including a plurality of geometric objects;
• identifying a plurality of repetitive cells of said input layout database, said repetitive cells being associated with the repetitive sub-circuits;
• selecting a plurality of extraneous cells from said repetitive cells;
• and
• generating a synoptic layout database including all of said cells of said input layout database except said extraneous cells.

A process of verifying an integrated circuit (IC) design for a system having a plurality of repetitive sub-circuits, the process comprising the steps of:

• receiving an input layout database including a plurality of layout cells geometrically representing the IC design, each of said cells including a plurality of geometric objects;
• identifying a plurality of repetitive cells of said input layout database, said repetitive cells being associated with the repetitive sub-circuits;
• selecting a plurality of extraneous cells from said repetitive cells;
• and
• generating a synoptic layout database including all of said cells of said input layout database except said extraneous cells;
• extracting a circuit net-list from said synoptic layout database;
• and
• processing said circuit net-list to verify characteristics of said integrated circuit.

A process of generating a synoptic layout database for efficient layout parasitic extraction and circuit simulation in post-layout verification of an integrated circuit (IC) design for a system having a plurality of repetitive sub-circuits, the process comprising the steps of:

• receiving an input layout database including a plurality of layout cells geometrically representing the IC design, each of said cells including a plurality of geometric objects;
• identifying a plurality of repetitive cells of said input layout database, said repetitive cells being associated with the repetitive subcircuits;
• and
• generating a synoptic layout database including less than all of said repetitive cells.