Back to results
US 6,289,409 B1Granted
Microcontroller with flexible interface to external devices
AssigneeInfineon Technologies North America Corp.
InventorTommaso Bacigalupo
Life of this patent
Estimating the term…
Abstract
A semiconductor device is disclosed that has a plurality of I/O pins that are configurable to selectively output three sets of signals selected from the group consisting of (i) a read enable signal and a write enable signal, (ii) a combined read and write enable signal, (iii) a read enable signal and a pair of byte write enable signals, and (iv) a row address strobe signal, and a column address strobe signal.
Claims3
A semiconductor device comprising:
- an external bus unit arranged to receive a selected address location selected from a group of address location consisting of:
- a first set of address locations associated with a first external device configured to receive a first set of signal(s) selected from a group of signals consisting of (i) a read enable signal and a write enable signal, (ii) a combined read and write enable signal, (iii) a read enable signal and a pair of byte write enable signals, and (iv) a row address strobe (RAS) signal and a column address strobe (CAS) signal,
- a second set of address locations associated with a second external device configured to receive a second set of signal(s) selected from the group consisting of (i) a read enable signal and a write enable signal, (ii) a combined read and write enable signal, (iii) a read enable signal and a pair of byte write enable signals, and (iv) a row address strobe (RAS) signal and a column address strobe (CAS) signal, and
- a third set of address locations associated with a third external device configured to receive a third set of signal(s) selected from the group consisting of (i) a read enable signal and a write enable signal, (ii) a combined read and write enable signal, (iii) a read enable signal and a pair of byte write enable signals, and (iv) a row address strobe (RAS) signal and a column address strobe (CAS) signal, wherein the first, second, and third set of signals are different from each other;
- and
- a plurality of I/O pins configurable for interfacing with the first, second, and/or third external device,
- wherein the external bus unit is further arranged to output at least one of
- the first set of signals when the selected address location is within the first set of address locations,
- the second set of signals when the selected address location is within the second set of address locations, and
- the third set of signals when the selected address location is within the third set of address locations.
7 more elements
Dependencies are inferred from the claim text.