Optimizing the performance of asynchronous bus bridges with dynamic transactions
AssigneeVLSI Technology, Inc.
InventorsPeter Chambers, Swaroop Adusumilli, Subramanian S. Meiyappan
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AssigneeVLSI Technology, Inc.
InventorsPeter Chambers, Swaroop Adusumilli, Subramanian S. Meiyappan
Estimating the term…
A system and method for completing a read transaction between an initiator device and a host memory device in a computer system, in which the present invention optimizes the retry behavior of the initiator device and a target device. The system of the present invention includes a bus bridge device, wherein the bus bridge device includes a target device coupled to the initiator device via a bus; the host memory device coupled to the bus bridge device; and a timer mechanism coupled to the target device. The initiator device is adapted to initiate a present read transaction via the target device, such that an access is asserted between the initiator device and the target device. The timer mechanism is adapted to measure target latency for one or more read transactions preceding the present read transaction, and the timer mechanism is further adapted to use the target latency to calculate a dynamic target latency period. The target device is adapted to maintain the access to the initiator device during the dynamic target latency period. Thus, in accordance with the present invention, the target latency is dynamically measured and used to optimize the retry behavior of the initiator and target devices.
A system for completing a present read transaction between an initiator device and a host memory device in a computer system, said system comprising:
A system for completing a present read transaction between an initiator device and a host memory device in a computer system, said system comprising:
In a peripheral component interconnect (PCI) bus system comprising a PCI initiator device coupled to a host memory device via a bus bridge device, said bus bridge device comprising a timer mechanism coupled to a PCI target device, a method for completing a present read transaction between said PCI initiator device and said host memory device, said method comprising the steps of:
Dependencies are inferred from the claim text.