Method and apparatus for analyzing correlation for semiconductor chips
AssigneeFujitsu Limited
InventorHiroaki Sekine
Life of this patent
Estimating the term…
Loading patent…
AssigneeFujitsu Limited
InventorHiroaki Sekine
Estimating the term…
A systematic yield Ysi is obtained from a yield Yi, Wafer data through are sorted in numeric order of a monitored quantity X, the sorted data is classified into m groups each having approximately equal number of data, the central value is obtained for each of X and Ys in the respective wafer groups, a correlation coefficient between X and Ys is calculated for the central values, and if the coefficient is greater than a predetermined value, a regression equation of Ys with respect to X is determined. The processes of the steps 30 through 34 are performed for a number of monitored quantities. In a case where the coefficient of the correlation between X and Ys is more than a predetermined value, this X is selected and a multiple regression equation of Ys with respect to only the selected ones is determined.
A method for analyzing a correlation for semiconductor chips, comprising the steps of:
A method for analyzing a correlation for semiconductor chips, comprising the steps of:
A semiconductor chip yield adjusting method, comprising the steps of:
A semiconductor chip yield adjusting method, comprising the steps of:
A storage medium having program stored therein, said program comprising the steps of:
An apparatus for analyzing a correlation for semiconductor chips, comprising a computer having program installed therein, said program comprising the steps of:
Dependencies are inferred from the claim text.