US 6,289,138 B1 · General image processor

Abstract

The present invention relates to an image processor (242) comprising a control register block (1470), a decoding block (1468), a data object processor (1462), and flow control logic. The control register block (1470) stores all the relevant information about the image processing operation. The decoding block (1468) decodes the information into configuration signals, which configure an input data object interface (1460). The input data object interface (1460) accepts and stores data objects from outside, and distributes these data objects to the data object processor (1462). For some image processing operations, the input data object interface (1460) may also generate addresses for data objects, so that the source of these data objects can provide the correct data objects. The data object processor (1462) performs arithmetic operations on the data objects received. The flow control logic controls the flow of data objects within the data object processing logic (1462). More particularly, the data object processor (1462) can comprise a number of identical data object sub-processors, each of which processes part of an incoming data object.

Claims40

Dependent claims

An apparatus for performing image processing operations on data objects, said apparatus including:

data source means for providing a stream of said data objects;
a plurality of operand source means for providing streams of operand objects, or providing operand objects in response to an address presented;
instruction means for selecting an image processing operation, and enabling or disabling a plurality of options in said image processing operation;
a configuration register for storing said image processing operation and options;
a register file for storing information necessary for performing said image processing operation;
decoding means connected to said configuration register for decoding said image processing operation and options;
a control signal register connected to said decoding means for storing the output of said decoding means;
input interface means, connected to said control signal register, said register file, said data source means and said plurality of said operand source means, for:
(a) accepting, storing and rearranging said data objects from said data source means, and said operand objects from said operand source means, in accordance with the output of said control signal register,
(b) generating addresses for said operand objects, in accordance with the output of said control signals register and said register file, and
(c) updating said information in said register file to reflect a current status of the image processing operation;
processing means, connected to said input interface means, said register file, and said control signal register, for performing arithmetic operations on the output of said input interface means in accordance with the output of said control signals register and said register file to produce processed data objects;
and
data destination means connected to said processing means for receiving said processed data objects.

11 more elements

An apparatus for performing compositing between two streams of pixels and a stream of attenuation values, said apparatus including:

data source means for providing a first one of said streams of pixels;
first operand source means for providing a second one of said streams of pixels;
second operand source means for providing said stream of attenuation values;
instruction means for enabling or disabling a plurality of options in compositing operations;
a configuration register for storing a compositing operation and said options of said instruction means;
register file for storing information necessary for performing compositing operations;
decoding means connected to said configuration register for decoding said options and said compositing operation;
a control signal register connected to said decoding means for storing the output of said decoding means;
input interface means, connected to said control signal register, said register file, said data source means, said first operand source means and said second operand source means, for:
(a) accepting, storing and rearranging pixels from said data source means and said first operand source means, and attenuation values from said second operand source means in accordance with an output of said control signal register,
(b) generating a stream of data objects to replace the second stream of pixels from said first operand source in accordance with the output of said control signal register and said register file, and
(c) updating said information in said register file to reflect a current status of the compositing operation;
processing means, connected to said input interface means, said register file, and said control signal register, for performing arithmetic operations on an output of said input interface means in accordance with the output of said control signal register and said register file to produce composited pixels;
and
data destination means connected to said processing means for receiving said composited pixels.

12 more elements

An apparatus for performing general color space conversion on streams of interval values, fraction values, and colour table values, said apparatus including:

data source means for providing said interval and fraction values;
operand source means for providing said color table values in response to said interval values presented;
instruction means for enabling or disabling a plurality of options for general color space conversion;
a configuration register for storing instruction means;
decoding means connected to said configuration register for decoding said instruction means;
a control signal register connected to said decoding means for storing the output of said decoding means;
input interface means, connected to said control signal register, said data source means, and said operand source means, for:
(a) accepting, storing, rearranging and outputting said interval values and said fraction values from said data source means in accordance with the output of said control signal register, and
(b) fetching said color table values from said operand source means using said interval value as an address, and storing, rearranging and outputting said color table values in accordance with the output of said control signal register;
processing means, connected to said input interface means and said control signal register, for performing arithmetic operations on the output of said input interface means in accordance with the output of said control signal register to produce a result color;
and
data destination means connected to said processing means for receiving the result color.

9 more elements

An apparatus for applying an affine image transformation on a source image, said apparatus including:

data source means for providing a kernel descriptor and weights of a weighting function;
first operand source means for providing index table values from a index table of said source image in response to an index table address presented;
second operand source means for providing at least one pixel of said source image in response to a pixel address presented;
an instruction means for enabling or disabling a plurality of options of said affine image transformation;
a configuration register for storing instruction means;
decoding means connected to said configuration register for decoding said instruction means;
a control signal register connected to said decoding means for storing an output of said decoding means;
a register file for storing information necessary for performing said affine image transformation;
input interface means connected to said control signal register, said register file, said data source means, and said operand source means for:
(a) accepting and storing said kernel descriptor and said weights of said weighting function from said data source means in accordance with the output of said control signal register,
(b) generating coordinates of pixels to be fetched from said source image in accordance to said kernel descriptor and outputs of said register file and said control signal register,
(c) calculating index table addresses from coordinates and the output of said register file,
(d) fetching index table entries from said first operand source means,
(e) calculating a pixel address from said index table entry and said coordinates,
(f) fetching at least one of pixels from said second operand means, and storing and rearranging said pixels in accordance with the output of said control signals register;
processing means, connected to said input interface means, said register file and said control signal register, for performing a plurality of arithmetic operations on the output of said input interface means in accordance with the output of said control signal register to produce a result pixel;
and
data destination means connected to said processing means for receiving the result pixel.

15 more elements

An apparatus for applying a convolution using a convolution matrix to a source image, said apparatus including:

data source means for providing a kernel descriptor and coefficients of said convolution matrix;
first operand source means for providing index table values from an index table of said source image in response to an index table address presented;
second operand source means for providing pixels of said source image in response to a pixel address presented;
an instruction means for enabling or disabling a plurality of options in convolution;
a configuration register for storing said instruction means;
decoding means connected to said configuration register for decoding said instruction means;
a control signal register connected to said decoding means for storing the output of said decoding means;
a register file for storing information necessary for performing an affine image transformation;
an input interface means, connected to said control signal register, said register file, said data source means, and said operand source means, for:
(a) accepting and storing said kernel descriptor and said weights of a weighting function from said data source means in accordance with the output of said control signal register,
(b) generating coordinates of pixels to be fetched from said image in accordance to said kernel descriptor and outputs of said register file and said control signal register,
(c) calculating index table addresses from said coordinates and the output of said register file,
(d) fetching index table entry from said first operand source means,
(e) calculating pixel address from said index table entry and said coordinates,
(f) fetching a plurality of pixels from said second operand means, and storing and rearranging said pixels in accordance with the output of said control signals register;
processing means, connected to said input interface means, said register file and said control signal register, for performing arithmetic operation on the output of said input interface means in accordance with the output of said control signal register to produce a result pixel;
and
data destination means connected to said processing means for receiving the result pixel.

15 more elements

An apparatus for performing a linear colour space conversion on a stream of source data objects with a conversion matrix, said apparatus including:

data source means for providing said source data objects;
operand source means for providing a plurality of coefficients of said conversion matrix in response to a line number presented;
instruction means for enabling or disabling a plurality of options in linear color space conversion;
a configuration register for storing said instruction means;
decoding means connected to said configuration register for decoding said instruction means;
a control signal register connected to said decoding means for storing the output of said decoding means;
input interface means, connected to said control signal register, said data source means, and said operand source means, for:
(a) accepting, storing and outputting said source data objects from said data source means in accordance with the output of said control signals register,
(b) generating said line number to fetch a plurality of said coefficients from operand source means in accordance to said control signal register, and
(c) storing, rearranging and outputting said coefficients in accordance with the output of said control signals register;
processing means, connected to said input interface means and said control signal register, for performing a plurality of arithmetic operations on the output of said input interface means in accordance with the output of said control signal register to produce a result data object;
and
data destination means connected to said processing means for receiving the result data object.

10 more elements

Dependencies are inferred from the claim text.

General image processor

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General image processor

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Abstract

Claims40