Digital filter for rotation correction loop of a QPSK or QAM demodulator
AssigneeSTMicroelectronics S.r.l.
InventorJacques Meyer
Life of this patent
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Abstract
The present invention relates to a digital filter for a phase-locked loop receiving at least one input signal having a predetermined period, including an element of accumulation of frequency values receiving the output of a phase detector; and an element of accumulation of phase values receiving a weighted sum of the output of the phase detector and of the content of the element of accumulation of frequency values. Each of the accumulation elements includes several frequency or phase value storage locations, circuitry being provided for successively making operative the storage locations in the phase-locked loop during a period of the input signal.
Claims23
A digital filter for a phase-locked loop receiving at least one input signal, the at least one input signal being characterized by a predetermined period, including:
- a frequency value accumulation element receiving an output of a phase detector;
- and
- a phase value accumulation element receiving a weighted sum of the output of the phase detector and of the content of the frequency value accumulation element;
- wherein each of the accumulation elements includes several registers containing different initial values, which are connected in parallel, in turn to be, to operate as an accumulator during a fraction of one period characterizing the input signal.
A digital filter for a phase-locked loop circuit, said digital filter receiving at least one input signal of predetermined period and comprising:
- frequency value accumulation circuit receiving an output of a phase detector of the phase-locked loop circuit;
- said frequency value accumulation circuit comprising frequency memory means containing N locations of frequency value;
- phase value accumulation means receiving a weighted sum of the output of the phase detector and of the content of the frequency value accumulation circuit;
- said phase value accumulation means comprising phase memory means containing N locations of phase value;
- and
- means for setting at least said frequency memory means to separately stored different frequency values.
A digital filter for a phase-locked loop circuit, said digital filter receiving at least one input signal of predetermined period and comprising:
- frequency value accumulation circuit receiving an output of a phase detector of the phase-locked loop circuit;
- said frequency value accumulation circuit comprising frequency memory containing N locations of frequency value;
- phase value accumulation circuit receiving a weighted sum of the output of the phase detector and of the content of the frequency value accumulation circuit;
- said phase value accumulation circuit comprising phase memory circuit containing N locations of phase value;
- and
- a counter for setting at least said frequency memory to separately stored different frequency values.
A method of digital filtering for a phase-locked loop circuit in which there is received at least one input signal of predetermined period, said method comprising the steps of:
- providing a frequency value accumulation circuit receiving an output of a phase detector of the phase-locked loop circuit;
- said frequency value accumulation circuit including a frequency memory containing N locations of frequency value;
- providing a phase value accumulation circuit receiving a weighted sum of the output of the phase detector and of the content of the frequency value accumulation circuit;
- said phase value accumulation circuit comprising a phase memory containing N locations of phase value;
- and
- setting at least said frequency memory to separately stored different frequency values.
Dependencies are inferred from the claim text.