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US 6,288,969 B1Granted
Multi-port random access memory
AssigneeNortel Networks Limited
InventorsRobert George Gibbins, Garnet Frederick Randall Gibson, Steven William Wood
Life of this patent
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Abstract
Disclosed is an architecture of a RAM (random access memory) with BIST (built-in self test) or functional test function. The RAM has a memory cell for storing differential or single-ended binary data and bit line signals are fully differential or single-ended. Shadow write is applied to read only and read-write bit lines. With the test function, port-to-port bit line shorts and port-to-port word line shorts are sensitized.
Claims11
A multi-port RAM (random access memory) comprising:
- RAM cells of m rows by n columns, each RAM cell including storage means for storing differential binary data, the RAM cells being coupled to respective row and column lines of each port, m and n being integers;
- data write means for storing differential binary data in the RAM cells selected by signals on the row and column lines of a port;
- data read means for reading the differential binary data stored in the RAM cells selected by signals on the row and column lines of a port;
- and
- voltage driving means for applying a predetermined level voltage onto selected ones of the column lines in a shadow write mode.
2 more elements
Dependencies are inferred from the claim text.