Semiconductor integrated circuit exhibiting improved high speed performance without wait time in operation

A semiconductor integrated circuit having:

• a plurality of basic blocks, at least one of said basic blocks being selectively activated in accordance with at least two types of selective signals, and each of said plurality of basic blocks having at least a circuit block and at least a receiver circuit connected to said circuit block;
• and
• at least one signal generator connected to said plurality of basic blocks for generating said at least two types of selective signals, each of the selective signals including control signals having a same active level in order to transmit said at least two types of selective signals to said receiver circuit in an activated one of said basic blocks,
• wherein if said receiver circuit receives said at least two types of selective signals which individually include said control signals having the same level as each other, then said receiver circuit generates an output signal having the same level as said control signal, and if said receiver circuit receives said at least two types of selective signals which individually include said control signals having different levels from each other, then said receiver circuit generates the output signal having the same level as most recently received control signals which had the same level as each other.