Semiconductor memory device
AssigneeFujitsu Limited
InventorYoshiharu Kato
Life of this patent
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Abstract
A variation in substrate voltage VBB caused by a reduction of power supply voltage VDD when an operation mode is shifted to a data retention mode is detected, and a cycle of refresh operation during this varying period is shortened or a plurality of memory cells are refreshed simultaneously, thereby enhancing the electric charge retention ability of the memory cells during this transient period. After the transient period is elapsed, the refresh cycle is returned to the original operating cycle, and the power consumption during the data retention mode can be effectively reduced.
Claims22
A semiconductor memory device with a first operation mode operating at a first power supply voltage and a second operation mode for carrying out a refresh operation of memory cells at a second power supply voltage lower than the first power supply voltage, the semiconductor memory device comprising:
- a substrate voltage generating circuit for generating a substrate voltage applied to a substrate portion of a memory cell region;
- a refresh section for carrying out the refresh operation of the memory cells at a predetermined cycle in the first operation mode;
- and
- a refresh control section for controlling the refresh section so that the refresh operation is carried out at a first cycle which is shorter than the predetermined cycle during a varying period of the substrate voltage when the first operation mode is shifted to the second operation mode.
A semiconductor memory device with a first operation mode operating at a first power supply voltage and a second operation mode for carrying out a refresh operation of memory cells at a second power supply voltage lower than the first power supply voltage, the semiconductor memory device comprising:
- a substrate voltage generating circuit for generating a substrate voltage applied to a substrate portion of a memory cell region;
- a refresh section for carrying out the refresh operation of the memory cells at a predetermined cycle in the first operation mode;
- and
- a substrate voltage control circuit for connecting the substrate voltage to a predetermined voltage node during a varying period of the substrate voltage when the first operation mode is shifted to the second operation mode.
A semiconductor memory device with a first operation mode operating at a first power supply voltage and a second operation mode for carrying out a refresh operation of memory cells at a second power supply voltage lower than the first power supply voltage, the semiconductor memory device comprising:
- a substrate voltage generating circuit for generating a substrate voltage applied to a substrate portion of a memory cell region;
- a reduced voltage generating circuit for generating the second power supply voltage from the first power supply voltage;
- wherein the reduced voltage generating circuit reduces a level of the second power supply voltage in response to a variation of the substrate voltage during a varying period in which the first operation mode is shifted to the second operation mode.
A semiconductor memory device with a first operation mode operating at a first power supply voltage and a second operation mode for carrying out a refresh operation of a memory cell at a second power supply voltage lower than the first power supply voltage, the semiconductor memory device comprising:
- a substrate voltage generating circuit for generating a substrate voltage applied to a substrate portion of a memory cell region;
- a reduced voltage generating circuit for generating the second power supply voltage from the first power supply voltage;
- wherein the reduced voltage generating circuit reduces the first power supply voltage to the second power supply voltage after the substrate voltage reaches to a predetermined level when the first operation mode is shifted to the second operation mode.
A semiconductor memory device with a first operation mode operating at a first power supply voltage and a second operation mode for carrying out a refresh operation of memory cells at a second power supply voltage lower than the first power supply voltage, the semiconductor memory comprising:
- a substrate voltage generating circuit for generating a substrate voltage applied to a substrate portion of a memory cell region;
- wherein a driving ability of the substrate voltage generating circuit is increased during a period in which the second operation mode is shifted to the first operation mode.
Dependencies are inferred from the claim text.