US 6,288,961 B1 · Semiconductor memory device for reading charges stored in capacitor in memory cell and data reading method thereof

Abstract

A semiconductor memory device reads data corresponding to charges stored in a capacitor in a memory cell and rewrites the data. This semiconductor memory device removes charges stored in the capacitor in the memory cell to a bit line or absorbs charges stored in the bit line into the capacitor in the memory cell, thereby generating a potential difference between the bit line pair. This potential difference is sensed by a sense amplifier and rewritten. Before the sense amplifier is operated, the potential difference is generated between the bit line pair. The parasitic capacitances of the bit line pair during operation of the sense amplifier are substantially equalized, and in this state, the potential difference is sensed.

Claims4

Dependent claims

A semiconductor device comprising:

a word line;
first and second bit lines;
a plate line;
a memory cell connected to the word line, the plate line and the first bit line, the memory cell having a transistor for transferring charges and a capacitor for storing the charges;
a control circuit for generating second and third control signals in response to a first control signal;
a decoder circuit connected to the word line, for selecting the word line in accordance with a plurality of address signals, the decoder circuit setting the selected word line in an unselected state in response to the second control signal;
a sense amplifier connected to the first and second bit lines and activated in response to the third control signal;
and
a plate line decoder circuit for selecting the plate line based on the first control signal and the plate line control signal and setting the plate line in an unselected state before transition of the second control signal occurs.

6 more elements

A semiconductor memory device comprising:

a control circuit section for generating first to fourth control signals, transitions of the first to fourth signals sequentially taking place at first to fourth timings respectively;
a decoder circuit section for setting a word line in a selected state in accordance with a plurality of address signals and outputting a plate line control signal, in response to a transition of the first control signal, setting the selected word line in an unselected state in response to a transition of the second control signal, and setting the word line in a selected state in response to a transition of the fourth control signal;
a plate line decoder circuit for, in response to a transition of the first control signal, selecting the plate line in accordance with the plate line control signal output from the decoder circuit section;
a first bit line which is set to a predetermined potential in response to a transition of the first control signal;
a second bit line which is set to a predetermined potential in response to a transition of the first control signal;
a transistor circuit section having a transistor and a ferroelectric capacitor, the transistor having a gate connected to the word line and a current path one end of which is connected to the first bit line, the ferroelectric capacitor having electrodes one of which is connected to the other end of the current path of the transistor and the other end of which is connected to the plate line, the first bit line and the ferroelectric capacitor being electrically separated when the word line is set in the unselected state in response to a transition of the second control signal, the first bit line and the ferroelectric capacitor being electrically connected when the word line is set in the selected state in response to a transition of the fourth control signal;
and
a sense amplifier section for amplifying a potential difference between the first bit line and the second bit line in response to a transition of the third control signal,
wherein the plate line decoder circuit selects the plate line in accordance with the plate line control signal, in response to the transition of the first control signal, and sets the plate line in the unselected state in response to the transition of the second control signal.

6 more elements

A semiconductor memory device comprising:

a control circuit section for generating first to fourth control signals, transitions of the first to fourth sequentially taking place at first to fourth timings respectively;
a decoder circuit section for setting a word line in a selected state in accordance with a plurality of address signals and outputting a plate control signal, in response to a transition of the first control signal, setting the selected word line in an unselected state in response to a transition of the second control signal, and setting the word line in a selected state at the fourth timing in response to a transition of the fourth control signal;
a plate line decoder circuit for, in response to a transition of the first control signal, selecting the plate line in accordance with the plate line control signal output from the decoder circuit section;
a first bit line which is set to a predetermined potential at the first timing in response to a transition of the first control signal;
a second bit line which is set to a predetermined potential at the first timing in response to a transition of the first control signal;
a transistor circuit section having a transistor and a capacitor, the transistor having a gate connected to the word line and a current path one end of which is connected to the first bit line, the capacitor having electrodes one of which is connected to the other end of the current path of the transistor and the other of which is connected to the plate line, the first bit line and the capacitor being electrically separated when the word line is set in the unselected state in response to a transition of the second control signal, the first bit line and the capacitor being electrically connected when the word line is set in the selected state in response to a transition of the fourth control signal;
and
a sense amplifier section for amplifying a potential difference between the first bit line and the second bit line in response to a transition of the third control signal
wherein the plate line decoder circuit selects the plate line in accordance with the plate line control signal, in response to the transition of the first control signal, and sets the plate line in the unselected state in response to the transition of the second control signal.

6 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device for reading charges stored in capacitor in memory cell and data reading method thereof

Life of this patent

Semiconductor memory device for reading charges stored in capacitor in memory cell and data reading method thereof

Life of this patent

Abstract

Claims4