Bias circuit for read amplifier circuits for memories

A bias circuit for a sense amplifier circuit for a memory comprising:

• a capacitive load connected to a first voltage reference;
• at least one first circuit branch connected to said capacitive load for driving said capacitive load with a reference current so that said capacitive load is charged to the first voltage reference, said at least one first circuit branch comprising a pair of transistors connected between the first voltage reference and a second voltage reference;
• at least one reference current amplifier branch for amplifying the reference current in said at least one first circuit branch;
• and
• a control circuit connected between said at least one reference current amplifier branch and said capacitive load for controlling charging of said capacitive load.

A memory device comprising:

• at least one read circuit;
• and
• at least one bias circuit connected to said at least one read circuit for biasing thereof, and comprising
• a capacitive load connected to a first voltage reference,
• at least one first circuit branch connected to said capacitive load for driving said capacitive load with a reference current so that said capacitive load is charged to the first voltage reference, said at least one first circuit branch comprising a pair of transistors connected between the first voltage reference and a second voltage reference,
• at least one reference current amplifier branch for amplifying the reference current in said at least one first circuit branch, and
• a control circuit connected between said at least one reference current amplifier branch and said capacitive load for controlling charging of said capacitive load.

A method for biasing a sense amplifier circuit for a memory comprising:

• charging a capacitive load to a first voltage reference with a reference current using at least one first branch circuit comprising a pair of transistors connected between the first voltage reference and a second voltage reference;
• amplifying the reference current in the at least one first circuit branch using at least one reference current amplifier branch;
• and
• controlling charging of the capacitive load using a control circuit connected between the at least one reference current amplifier branch and the capacitive load.