Controlling the precharge operation in a DRAM array in a SRAM interface

A control circuit for controlling the operation of a DRAM array having a plurality of rows and columns of memory cells, sense amplifiers associated with the memory cells, and word lines, bit lines, column switches, and bit equalization lines associated with the memory cells, the control circuit comprising:

• an input terminal for receiving an x-address associated with said word lines for a new operation cycle;
• a comparison circuit coupled to said input terminal, said comparison circuit determines if said x-address is different from a preceding x-address for a preceding operation cycle;
• a timing generator coupled to said comparison circuit, said timing generator outputs an equalization enable signal and a sense latch disable signal when said x-address is different from said preceding x-address and outputs an equalization disable signal and a sense latch enable signal when said x-address is the same as said preceding x-address.

A memory system including a DRAM array coupled to an SRAM interface, said memory system comprising:

• an activity monitor circuit that receives an x-address associated with a word line for a new operation cycle of said DRAM array, said activity monitor circuit having a comparison circuit that compares said x-address with an old x-address for a preceding operation cycle of said DRAM array and having an output terminal that outputs a signal indicating when said x-address is the same as said old x-address;
• and
• a timing control circuit having an input terminal that receives said signal indicating when said x-address is the same as said old x-address, said timing control circuit having a timing element that simulates a precharge cycle, said timing control circuit having an output terminal that outputs a sense latch enable signal after said simulated precharge cycle.