Semiconductor device having test function
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTetsushi Tanizaki, Tetsuo Kato, Mikio Asakura, Yasuhiro Konishi, Takayuki Miyamoto
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Abstract
A semiconductor device according to the present invention includes a plurality of test mode circuits. Each test mode circuit includes a plurality of decode circuits decoding an input signal and a plurality of latch circuits. Each decode circuit generates a test mode signal. The test mode signals are held in the latch circuits. Each test mode circuit further includes decode circuits outputting a group reset signal for resetting a corresponding latch circuit. Thus, a plurality of test mode signals can be combined arbitrarily and serially.
Claims11
A semiconductor device, comprising:
- an internal circuit;
- and
- a plurality of test mode setting circuits receiving an input signal,
- said plurality of test mode setting circuits each including
- a test mode signal generation circuit generating a test mode signal for setting a test mode of said internal circuit according to said input signal, and
- a hold circuit holding a state of said test mode signal.
A semiconductor device, comprising:
- an internal circuit;
- a plurality of test mode setting circuits receiving an input signal;
- and
- a test mode detection circuit generating a test mode enable signal according to said input signal,
- said plurality of test mode setting circuits each including
- a test mode signal generation circuit responsive to said test mode enable signal for generating a test mode signal for setting a test mode of said internal circuit according to said input signal, and
- a hold circuit holding a state of said test mode signal.
A semiconductor device, comprising:
- an internal circuit;
- and
- a plurality of test mode setting circuits receiving an input signal including a plurality of bits,
- said plurality of test mode setting circuits each including
- a test mode signal generation circuit generating a test mode signal for setting a test mode of said internal circuit according to said input signal, and
- a hold circuit holding a state of said test mode signal.
Dependencies are inferred from the claim text.