Methods and systems for testing integrated circuit memory devices by overlappiing test result loading and test result analysis

A method of testing integrated circuit memory devices by performing a series of comparison tests between test pattern data that is input into a memory device and resultant data that is output from the memory device, the series of comparison tests including a preceding comparison test and a succeeding comparison test which follows the preceding comparison test, the method comprising the steps of:

• loading into a first defect interpretation memory, results of the preceding comparison test between test pattern data that is input into a memory device and resultant data that is output from the memory device;
• automatically switching to a second defect interpretation memory and loading therein results of the succeeding comparison test while simultaneously analyzing the results from the preceding comparison test in the first defect interpretation memory;
• automatically switching back to the first defect interpretation memory and loading therein results of a next succeeding comparison test while simultaneously analyzing the results from the succeeding comparison test in the second defect interpretation memory;
• and
• repeatedly performing the steps of automatically switching and automatically switching back to thereby simultaneously test a memory device and analyze memory test results.

A system for testing integrated circuit memory devices by performing a series of comparison tests between test pattern data that is input into a memory device and resultant data that is output from the memory device, the series of comparison tests including a preceding comparison test and a succeeding comparison test which follows the preceding comparison test, the system comprising:

• first and second defect interpretation memories;
• means for loading into the first defect interpretation memory, results of a preceding comparison test between test pattern data that is input into a memory device and resultant data that is output from the memory device;
• means for automatically switching to the second defect interpretation memory and for loading therein results of the succeeding comparison test while simultaneously analyzing the results from the preceding comparison test in the first defect interpretation memory;
• and
• means for automatically switching back to the first defect interpretation memory and loading therein results of a next succeeding comparison test while simultaneously analyzing the results from the succeeding comparison test in the second defect interpretation memory.

A memory testing system comprising:

• a pattern generator that loads test patterns into a memory device under test;
• a logic comparator that is responsive to the pattern generator and to the memory device under test, to compare test pattern data that is output from the memory device under test and the test patterns, to generate information concerning defects in the memory device under test;
• first and second defect interpretation memories that are responsive to the logic comparator, to store the information concerning defects in the memory device under test;
• a defect interpretation unit that is responsive to the first and second defect interpretation memories to interpret the defects in the memory device under test based on the information concerning defects in the memory device under test that is stored in the first and second defect interpretation memories;
• and
• a switching unit that alternatingly couples the first and second defect interpretation memories to the defect interpretation unit to thereby alternatingly interpret the defects in the memory device under test based on the information concerning defects in the memory device under test that is stored in the first and second defect interpretation memories.

A memory testing system comprising:

• means for loading test patterns into a memory device under test;
• means for comparing test pattern data that is output from the memory device under test and the test patterns, to generate information concerning defects in the memory device under test;
• first and second defect interpretation memory means for storing the information concerning defects in the memory device under test;
• means for interpreting the defects in the memory device under test based on the information concerning defects in the memory device under test that is stored in the first and second defect interpretation memory means;
• and
• means for alternatingly coupling the first and second defect interpretation memory means to the means for interpreting to thereby alternatingly interpret the defects in the memory device under test based on the information concerning defects in the memory device under test that is stored in the first and second defect interpretation memory means.