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US 6,288,952 B1Granted
System for improved memory cell access
AssigneeMicron Technology, Inc.
InventorHua Zheng
Life of this patent
Estimating the term…
Abstract
A voltage booting circuit for booting the switching signal applied to a column access passgate is employed to reduce the voltage drop across the passgate. Reduction of the voltage dropped across the passgate results in faster read and write times and improved noise margin. In one application the booted voltage is used only during a write operation, but not during a read. In another application, the booted voltage is used during both operations.
Claims27
A dynamic random access memory (DRAM) comprising:
- an array of memory cells;
- an access transistor connected to one of the memory cells and a digit line, such that the access device has a drain connected to the digit line, and a source connected to the one memory cell;
- a word line coupled to a gate connection of the access, transistor;
- an p-channel transistor having a source connection, a drain connection and a gate connection, wherein the source connection is coupled to the digit line, and wherein the drain is selectively coupled to either a write driver circuit or an I/O sense amplifier circuit;
- and
- a voltage boot circuit connected to the gate of the p-channel transistor, the voltage boot circuit being configured to produce an internal booted column select signal having a negative voltage that is at least a threshold voltage of the p-channel transistor below zero volts.
3 more elements
A dynamic random access memory (DRAM) comprising:
- an array of memory cells arranged in rows and columns, each memory cell comprising a storage capacitor and an access transistor;
- a p-channel transistor having a first port coupled to at least one of the memory cells, and a second port connected to memory cell access read and write circuitry;
- and
- a column select circuit connected to a gate connection of the p-channel transistor, the column select circuit comprising a column boot circuit for producing an internal column select signal having a negative voltage that is at least a threshold voltage of the p-channel transistor below zero volts.
1 more element
A static memory comprising:
- an array of memory cells;
- an access transistor connected to one of the memory cells and digit line, such that the access device has a drain connected to the digit line, and a source connected to the one memory cell;
- a word line coupled to a gate connection of the access transistor;
- a p-channel transistor having a source connection, drain connection and a gate connection, the source connection is coupled to the digit line, and the drain is selectively coupled to either a write driver circuit or an I/O sense amplifier circuit;
- and
- a voltage boot circuit connected to the gate of the p-channel transistor, the voltage boot circuit configured to produce an internal booted column select signal having a negative voltage which is at least a threshold voltage of the p-channel transistor below zero volts.
3 more elements
A static memory comprising:
- an array of memory cells arranged in rows and columns, each memory cell comprising a storage capacitor and an access transistor;
- a p-channel transistor having a first port coupled to at least one of the memory cells, and a second port connected to memory cell access read and write circuitry;
- and
- a column select circuit connected to a gate connection of the p-channel transistor, the column select circuit comprising a column boot circuit for producing an internal column select signal having a negative voltage that is at least a threshold voltage of the p-channel transistor below zero volts.
1 more element
An integrated circuit memory comprising:
- a node for receiving an external chip supply voltage;
- a plurality of memory cells for storing information;
- and
- a column select system comprising
- an access device including a gate connected to a word line, a drain connected to a digit line, and a source connected to one of the memory cells,
- a passgate comprising a p-channel transistor device including a first port connected to the digit line, a second port connected to a write driver, and an I/O sense amplifier, the write driver providing a voltage corresponding to the chip supply voltage, and a switchable gate, and
- a column driver connected to the switchable gate of the passgate, the column driver comprising column boot circuitry for producing an internal booted column select signal having a negative voltage that is at least a threshold voltage of the p-channel transistor below zero volts.
4 more elements
An integrated circuit memory comprising:
- a node for receiving an external chip supply voltage;
- a plurality of memory cells for storing information, the plurality of memory cells arranged in a plurality of columns;
- and
- a column select system comprising
- a passgate comprising a p-channel transistor device having a first port coupled to at least one of the memory cells, a second port connected to memory cell access electronics having writing and reading voltages approximately equal to the chip supply voltage, and a switchable gate;
- and
- a column select circuit connected to the switchable gate of the passgate, the column select circuit comprising column boot circuitry for producing an internal booted column select signal having a negative voltage that is at least a threshold voltage of the p-channel transistor below zero volts.
4 more elements
A method for accessing a column of a memory device having a node to receive an external chip supply voltage, the method comprising:
- generating an internal booted column select signal having a negative voltage that is at least a threshold voltage of a p-channel transistor device below zero volts, the p-channel transistor device acting as a passgate;
- and
- applying the internal booted column select signal to the passgate for activating the passgate to connect a memory cell in a memory array to memory cell access electronics.
A method for reading a memory cell, the method comprising:
- accessing the memory cell to couple data from the memory cell to a digit line;
- generating an internal booted column select signal having a negative voltage that is at least a threshold voltage of a p-channel transistor device below zero volts;
- and
- coupling the internal booted column select signal to activate a p-channel transistor having a first node coupled to the digit line and a second node coupled to data sense amplifier circuitry.
1 more element
A method for writing data to a memory cell, the method comprising:
- accessing the memory cell to couple the memory cell to a digit line;
- generating an internal booted column select signal having a negative voltage that is at least a threshold voltage of a p-channel transistor device below zero volts;
- and
- coupling the internal booted column select signal to activate a p-channel transistor having a first node coupled to the digit line and a second node coupled to write driver circuitry;
- and
- providing a data signal from the write driver circuit.
3 more elements
A column select system for an integrated circuit memory having an external chip supply voltage, said memory including a plurality of memory cells for storing information, said column select system comprising:
- an access device including
- a gate connected to a word line,
- a drain connected to a digit line, and
- a source connected to one of the memory cells;
- a passgate comprising a p-channel transistor device including
- a first port connected to the digit line,
- a second port connected to a write driver and an I/O sense amplifier, the write driver providing a voltage corresponding to the chip supply voltage, and
- a switchable gate;
- and
- a column driver connected to the switchable gate of the passgate, the column driver comprising column boot circuitry for producing an internal booted column select signal having a negative voltage that is at least a threshold voltage of the p-channel transistor device below zero volts.
7 more elements
A column select system for an integrated circuit memory having an external chip supply voltage, said memory including a plurality of memory cells for storing information, the plurality of memory cells configured in a plurality of columns, said column select system comprising:
- a passgate comprising a p-channel transistor device including
- a first port coupled to at least one of said memory cells,
- a second port connected to memory cell access electronics having writing and reading voltages approximately equal to the chip supply voltage, and
- a switchable gate;
- and
- a column select circuit connected to the switchable gate of the passgate, the column select circuit comprising column boot circuitry for producing an internal booted column select signal having a negative voltage that is at least a threshold voltage of the p-channel transistor device below zero volts.
3 more elements
Dependencies are inferred from the claim text.