Semiconductor memory device capable of generating offset voltage independent of bit line voltage
AssigneeNEC Corporation
InventorHiroki Koike
Life of this patent
Estimating the term…
Abstract
In a semiconductor memory device including a plurality of word lines, a plurality of pairs of bit lines, a plurality of memory cells, each connected between one of the word lines and one of the bit lines, and a plurality of sense amplifiers for amplifying the difference in potential between the pair of the bit lines, a plurality of offset circuits, is provided, for applying an offset voltage independent of voltages at the bit lines, to at least one of the pair of the bit lines to reduce the difference in potential between the pair of the bit lines before the sense amplifiers are operated.
Claims21
A semiconductor memory device comprising:
- a plurality of word lines;
- a plurality of bit lines organized in bit-line-pairs;
- a plurality of memory cells, each connected between one of said word lines and one of said bit lines;
- a plurality of sense amplifiers, each connected to a corresponding one of said bit-line-pairs, for amplifying a difference in potential between bit lines of said corresponding bit-line-pair;
- and
- a corresponding plurality of offset circuits, each correspondingly connected to said one corresponding bit-line-pair, for applying an offset voltage to at least one of said bit lines of said corresponding bit-line-pair to reduce the difference in potential between the bit lines of said corresponding bit-line-pair,
- said offset voltage being independent of voltages at said bit lines.
A ferroelectric random access memory device comprising:
- a plurality of word lines;
- a plurality of plate lines;
- a plurality of bit lines organized in bit-line-pairs;
- a plurality of memory cells of a one-transistor, one-ferroelectric-capacitor type, each connected to one of said word lines, one of said plate lines and one of said bit lines;
- a plurality of sense amplifiers, each connected to one of said bit-line-pairs, for amplifying a difference in potential between the bit lines of said bit-line-pair;
- and
- a corresponding plurality of offset circuits, each correspondingly connected to said one bit-line-pair, for applying an offset voltage to at least one bit line of said one bit-line-pair to reduce the difference in potential between the bit lines of said one bit-line-pair,
- said offset voltage being independent of voltage at said bit lines.
A ferroelectric random access memory device comprising:
- a plurality of bit-line-pairs;
- and
- a plurality of offset circuits, each connected to a corresponding one of said bit-line-pairs, for applying an offset voltage that reduces a voltage difference during a test mode between the two bit lines of said corresponding bit-line-pair, wherein said offset voltage comprises a constant voltage unaffected by a voltage level on either of said two bit lines.
An offset circuit in a ferroelectric random access memory device having a plurality of bit lines organized in bit-line-pairs, comprising:
- a transistor switch controlled by a test mode input command;
- and
- a constant voltage source that is unaffected by a voltage on any of said bit lines, such that said constant voltage reduces a voltage difference between the bit lines of at least one selected said bit-line-pairs during said test mode.
A method of testing a ferroelectric random access memory device having a plurality of bit lines organized in bit-line-pairs, said method comprising:
- injecting, during a test mode, a voltage offset to at least one of the two bit lines of at least one selected one of said bit-line-pairs to reduce a voltage difference between said two bit lines, wherein said voltage offset is derived from a source that is unaffected by a voltage on any of said bit lines.
Dependencies are inferred from the claim text.