Semiconductor memory device including an SOI substrate
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHideto Hidaka, Katsuhiro Suma, Takahiro Tsuruda
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Abstract
A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.
Claims10
A semiconductor memory device comprising a plurality of MOS transistors,
- wherein said plurality of MOS transistors are formed on an SOI substrate,
- each of said plurality of MOS transistors including a source region, a drain region, and a body region located between said source region and said drain region,
- wherein the body region of at least one MOS transistor of said plurality of MOS transistors is supplied with a variable potential which becomes a reverse potential with respect to a PN junction between one of said source and drain regions and said body region.
A semiconductor memory device comprising a plurality of MOS transistors and output terminals, for storing data and externally providing the stored data via said output terminals,
- wherein said plurality of MOS transistors are formed on an SOI substrate, each of said plurality of MOS transistors including a source region, a drain region and a body region located between said source region and said drain region,
- one of said plurality of MOS transistors having a source region connected to one of said output terminals and to its body region.
A semiconductor memory device to which a predetermined power supply voltage is supplied, including a plurality of MOS transistors,
- wherein said plurality of MOS transistors are formed on an SOI substrate,
- wherein one of said plurality of MOS transistors to which a voltage higher than said power supply voltage is supplied has a body region being electrically fixed and located between its source and drain regions.
A semiconductor memory device comprising a plurality of MOS transistors and an input/output line, for reading/writing data via said input/output line,
- wherein said plurality of MOS transistors and said input/output line are formed on an SOI substrate, each of said plurality of MOS transistors including a source region, a drain region, and a body region located between said source region and said drain region,
- wherein one of said plurality of MOS transistors has a source region or a drain region connected to said input/output line, and a body region that is electrically fixed.
A semiconductor memory device comprising a plurality of MOS transistors,
- wherein said plurality of MOS transistors are formned on an SOI substrate, and
- wherein the body region located between a source region and a drain region of a MOS transistor included in an input buffer for receiving an external signal to provide an internal signal out of said plurality of MOS transistors is electrically fixed.
A semiconductor memory device comprising a plurality of MOS transistors,
- wherein said plurality of MOS transistors are formed on an SOI substrate,
- wherein the body region located between a source region and a drain region of a MOS transistor at an output stage for externally providing a signal out of said plurality of MOS transistors is electrically fixed.
A semiconductor memory device comprising a plurality of MOS transistors, wherein a plurality of N channel MOS transistors out of said plurality of MOS transistors are connected in series between an output node for providing a signal and a ground node,
- wherein said plurality of MOS transistors are formed on an SOI substrate,
- wherein the body region located between a source region and a drain region of at least one N channel MOS transistor other than an N channel MOS transistor having a source region directly connected to said ground node out of said plurality of N channel MOS transistors is electrically biased.
Dependencies are inferred from the claim text.