Wired address compare circuit and method
AssigneeCypress Semiconductor Corporation
InventorsJames W. Lutley, Neil P. Raftery, Jonathan F. Churchill, Kenneth A. Maher
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Abstract
An apparatus comprising a first register, a second register and a plurality of compare circuits. The first register may be configured to store a plurality of first address bits. The second register may be configured to store a plurality of second address bits. The plurality of compare circuits may each be configured to generate an output signal in response to one of said plurality of first address bits and one of said plurality of second address bits. The output signals are generally each at either (i) the same logic state or (ii) a high-Z state.
Claims18
An apparatus comprising:
- a first register configured to store a plurality of first address bits;
- a second register configured to store a plurality of second address bits;
- and
- a plurality of compare circuits, each configured to generate an output signal in response to one of said plurality of first address bits and one of said plurality of second address bits, wherein said output signals are each at either (i) the same logic state or (ii) a high-Z state.
An apparatus comprising:
- means for storing a plurality of first address bits;
- means for storing a plurality of second address bits;
- and
- means for generating a plurality of output signals, each in response to one of said plurality of first address bits and one of said plurality of second address bits;
- and
- means for generating a global output signal in response to said plurality of output signals, a control signal, and a power-on-reset signal, wherein said output signals are each at either (i) the same logic state or (ii) a high-Z state.
A method for comparing a plurality of bits of an address comprising the steps of:
- (A) storing a plurality of first address bits;
- (B) storing a plurality of second address bits;
- (C) generating a plurality of output signals in response to one of said plurality of first address bits and one of said plurality of second address bits, wherein said output signals are each at either (i) the same logic state or (ii) a high-Z state;
- and
- (D) generating a global output signal in response to said plurality of output signals, a control signal and power-on-reset signal.
Dependencies are inferred from the claim text.