Method for programming and reading 2-bit p-channel ETOX-cells with non-connecting HSG islands as floating gate
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorMin-hwa Chi
Life of this patent
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Abstract
A method of reading a 2-bit p-channel memory cell having a p+ drain, a p+ source, a control gate, and a floating gate formed from non-connecting hemispherical silicon grain (HSG) islands. The p+ drain and the p+ source is formed in an n-well. The method comprises: applying a positive voltage to the control gate to generate a gate induced drain leakage (GIDL) current; and measuring a drain GIDL current at the drain and a source GIDL current at the source simultaneously to determine the 2-bit data stored in the memory cell.
Claims12
A method of simultaneously reading a 2-bit p-channel memory cell having a p+ drain, a p+ source, a control gate, and a floating gate formed from non-connecting hemispherical silicon grain (HSG) islands, said p+ drain and said p+ source being formed in an n-well, the method comprising:
- applying a positive voltage to said control gate to generate a gate induced drain leakage (GIDL) current;
- and
- measuring a drain GIDL current at said drain and a source GIDL current at said source to determine the data stored in said memory cell.
A method of simultaneously reading a 2-bit p-channel memory cell having a p+ drain, a p+ source, a control gate, and a floating gate formed from non-connecting hemispherical silicon grain (HSG) islands, said p+ drain and said p+ source being formed in an n-well, the method comprising:
- applying a positive voltage to said control gate to generate a gate induced drain leakage (GIDL) current;
- and
- measuring a drain GIDL current at said drain and a source GIDL current at said source to determine the data stored in said memory cell, wherein it is determined that:
- said memory cell holds a “00” data if said drain GIDL current and said source GIDL current is above a predetermined threshold;
- said memory cell holds a “11” data if said drain GIDL current and said source GIDL current is below said predetermined threshold;
- said memory cell holds a “10” data if said drain GIDL current is above said predetermined threshold and said source GIDL current is below said predetermined threshold;
- and
- said memory cell holds a “01” data if said source GIDL current is above said predetermined threshold and said drain GIDL current is below said predetermined threshold.
A method of simultaneously reading a 2-bit p-channel memory cell having a p+ drain, a p+ source, a control gate, and a floating gate formed from non-connecting hemispherical silicon grain (HSG) islands, said p+ drain and said p+ source being formed in an n-well, the method comprising:
- applying a positive voltage to said control gate to generate a gate induced drain leakage (GIDL) current;
- and
- measuring a drain GIDL current at said drain and a source GIDL current at said source to determine the data stored in said memory cell, wherein said p+ drain and said p+ source are held to zero volts.
A method of simultaneously programming a 2-bit p-channel memory cell having a p+ drain, a p+ source, a control gate, and a floating gate formed from non-connecting hemispherical silicon grain (HSG) islands, said p+ drain and said p+ source being formed in an n-well, the method comprising:
- applying a positive voltage to said control gate;
- and
- selectively applying a negative voltage to said p+ source or p+ drain to induce band-to-band tunneling induced hot electron (BBHE) injection into said floating gate.
A method of simultaneously programming a 2-bit p-channel memory cell having a p+ drain, a p+ source, a control gate, and a floating gate formed from non-connecting hemispherical silicon grain (HSG) islands, said p+ drain and said p+ source being formed in an n-well, the method comprising:
- applying a positive voltage to said control gate;
- and
- selectively applying a negative voltage to said p+ source or p+ drain to induce band-to-band tunneling induced hot electron (BBHE) injection into said floating gate, wherein
- if a digital “11” is to be stored in said memory cell, biasing both p+ source and p+ drain to said negative voltage;
- if a digital “00” is to be stored in said memory cell, biasing both p+ source and p+ drain to a zero voltage;
- if a digital “10” is to be stored in said memory cell, biasing said p+ source to said negative voltage and biasing said p+ drain to a zero voltage;
- and
- if a digital “01” is to be stored in said memory cell, biasing said p+ drain to said negative voltage and biasing said p+ source to a zero voltage.
A method of simultaneously programming a 2-bit p-channel memory cell having a p+ drain, a p+ source, a control gate, and a floating gate formed from non-connecting hemispherical silicon grain (HSG) islands, said p+ drain and said p+ source being formed in an n-well, the method comprising:
- applying a positive voltage to said control gate;
- and
- selectively applying a negative voltage to said p+ source or p+ drain to induce band-to-band tunneling induced hot electron (BBHE) injection into said floating gate, wherein
- if a digital “11” is to be stored in said memory cell, biasing both p+ source and p+ drain to a zero voltage;
- if a digital “00” is to be stored in said memory cell, biasing both p+ source and p+ drain to said negative voltage;
- if a digital “10” is to be stored in said memory cell, biasing said p+ drain to said negative voltage and biasing said p+ source to a zero voltage;
- and
- if a digital “01” is to be stored in said memory cell, biasing said p+ source to said negative voltage and biasing said p+ drain to a zero voltage.
Dependencies are inferred from the claim text.