Electrically erasable semiconductor non-volatile memory device having memory cell array divided into memory blocks

An electrically erasable semiconductor nonvolatile memory device comprising:

• a semiconductor substrate having a main surface;
• a memory cell array having a plurality of nonvolatile memory cells arranged in rows and columns, each of said memory cells including a field-effect transistor element having a first gate electrode, drain and source regions formed at the main surface of said semiconductor substrate and a second gate electrode, said second gate electrode being interposed between said first gate electrode and that part of the main surface of said semiconductor substrate, associated with each said field-effect transistor element, which lies between said drain and source regions;
• first decoder circuit means for controlling said first gate electrode of the field-effect transistor elements of said memory cells;
• first conductors formed over said semiconductor substrate and extended as word lines, respectively, in a first direction substantially parallel with said rows, the first gate electrodes of the field-effect transistor elements of memory cells on one row being connected in common with a respective one of said first conductors;
• second conductors formed over said semiconductor substrate and extended in a second direction substantially parallel with said columns, the drain regions of the field-effect transistor elements of memory cells on one column being connected in common with a respective one of said second conductors;
• second decoder circuit means for controlling accessing of said second conductors through ON and OFF control of a switching circuit;
• third conductors formed over the main surface of said semiconductor substrate and extended in said first direction so as to be substantially parallel with said rows, the source regions of the field-effect transistor elements of at least one row of memory cells being connected in common with a respective one of said third conductors;
• and
• means for selectively applying to said third conductors an information erasure signal, independently of said first decoder circuit means, in which simultaneous erasure of the memory cells connected to one or more word lines is effected by providing a potential difference between that of a third conductor, supplied with said information erasure signal, and said one or more word lines, supplied with a predetermined voltage, corresponding thereto and by said second decoder circuit means keeping said switching circuit in an OFF state, in an erase mode, such that the drain regions are not supplied with a power potential.

A substantially rectangular semiconductor chip having an electrically erasable semiconductor nonvolatile memory device and a plurality of connection pads including address signal pads and I/O pads in a peripheral portion at a main surface of the chip, said semiconductor memory device comprising:

• at least one semiconductor memory cell array each having a plurality of nonvolatile memory cells arranged in rows and columns and a plurality of word line conductors and a plurality of data line conductors, each of said memory cells being connected with one word line conductor and one data line conductor, address signal pads for relatively higher order digits and those for relatively lower order digits being substantially arranged near one and the other of a first pair of opposing outer peripheral edges of the rectangular chip which are directioned substantially parallel with said word line conductors, respectively, each of said memory cells including a field-effect transistor element having a first gate electrode, a second gate electrode and first and second semiconductor regions formed in said chip, said second gate electrode being interposed between said first gate electrode and that part of the main surface of said chip, associated with each said field-effect transistor element, which lies between said first and second semiconductor regions, said word line conductors being formed at the main surface of said chip and extended in a first direction substantially parallel with said rows, the first gate electrodes of field-effect transistor elements of memory cells on one row being connected in common with a respective one of said word line conductors, said data line conductors being formed at the main surface of said chip and extended in a second direction substantially parallel with said columns, the first semiconductor regions of field-effect transistor elements of memory cells on one column being connected in common with a respective one of said data line conductors, and erasure line conductors being formed at the main surface of said chip and extended in said first direction so as to be substantially parallel with said rows,
• wherein each array of said at least one semiconductor memory cell array includes a plurality of memory blocks, each memory block being comprised of plural rows of memory cells in which the second semiconductor regions of the field-effect transistor elements thereof are connected in common with a same one of said erasure line conductors, said erasure line conductors corresponding, respectively, to different ones of said memory blocks;
• a row address decoder, for electrical connection with said address signal pads for relatively higher order digits, covering a first plan view area of the main surface of the chip, adjacent a first end side which is directioned substantially parallel with said data line conductors, of a second plan view area which is for said semiconductor memory cell array;
• a column address decoder, covering a third plan view area of the main surface of said chip in the vicinity of said semiconductor memory cell array and near that outer peripheral edge of said chip where said address signal pads for lower order digits are arranged for electrical connection therewith;
• erasure means, covering a fourth plan view area of the main surface of said chip adjacent a second end side of said second plan view area, for said semiconductor memory cell array, which second end side is opposite the first end side thereof and which is directioned substantially parallel with said data line conductors, provided for electrical connection with at least a portion of said address signal pads for relatively higher order digits for selectively applying an information erasure signal to said semiconductor memory cell array,
• wherein said erasure means selectively applies an information erasure signal to said erasure line conductors, independently of said row address decoder, in which simultaneous erasure is effected of the memory cells within a selected memory block and said data line conductors are kept from being supplied with a power potential in an erase mode;
• and
• sense amplifier means, covering a fifth plan view area of the main surface of said chip adjacent that one of third and fourth opposite end sides of said second plan view area for said semiconductor memory cell array, which is directioned substantially parallel with said word line conductors, near that outer peripheral edge of said chip where said I/O pads are arranged for electrical connection therewith.

An electrically erasable semiconductor nonvolatile memory device comprising:

• a plurality of nonvolatile memory cells formed in a semiconductor substrate and arranged in an array of rows and columns, each of said memory cells including a field-effect transistor element having a floating gate, a control gate and first and second semiconductor regions;
• word line conductors extending in a first direction substantially parallel with said rows;
• data line conductors extending in a second direction substantially parallel with said columns, the control gates and first semiconductor regions of said memory cells being connected with said word line and data line conductors, respectively, to form said array, said array of nonvolatile memory cells consisting of a plurality of memory blocks,
• wherein each of said memory blocks includes at least one word line conductor and the memory cells connected thereto and a common conductor connected to the second semiconductor regions of the field-effect transistor elements of the memory cells in said each memory block and extending in said first direction substantially parallel with said word line conductors, each common conductor belonging to a respective one of said memory blocks and serving, in an erasing operation, as a path for electrons to be extracted from the floating gates of the field-effect transistor elements of the memory cells in the memory block with which the common conductor corresponds to, and each word line conductor belonging to a respective one of said memory blocks;
• and
• an erasure signal generator coupled to the common conductors,
• wherein said erasure signal generator is responsive to an externally supplied address signal to generate an erasure signal to be selectively applied to at least one of the common conductors, independently of selection signals supplied to said word line conductors, and
• wherein simultaneous erasure of memory cells connected to said at least one word line in a selected memory block is effected by providing a potential difference between that of said common conductor, supplied with the erasure signal, and each word line conductor, supplied with a predetermined voltage, corresponding to that memory block and keeping said data line conductors from being supplied with a power potential, in an erase mode.

An electrically erasable semiconductor nonvolatile memory device comprising:

• a semiconductor substrate having a main surface;
• a memory cell array having a plurality of nonvolatile memory cells arranged in rows and columns, each of said memory cells including a field-effect transistor element having a first gate electrode, first and second semiconductor regions formed at the main surface of said semiconductor substrate and a second gate electrode, said second gate electrode being interposed between said first gate electrode and that part of the main surface of said semiconductor substrate, associated with each said field-effect transistor element, which lies between said first and second semiconductor regions;
• decoder circuit means for controlling said first gate electrode of the field-effect transistors of said memory cells;
• first conductors formed over said semiconductor substrate and extended in a first direction substantially parallel with said rows, the first gate electrodes of field-effect transistor elements of memory cells on one row being connected in common with a respective one of said first conductors;
• second conductors formed over said semiconductor substrate and extended in a second direction substantially parallel with said columns, the first semiconductor regions of field-effect transistor elements of memory cells on one column being connected in common with a respective one of said second conductors;
• third conductors formed over the main surface of said semiconductor substrate and extended in said first direction so as to be substantially parallel with said rows, the second semiconductor regions of at least one row of field-effect transistor elements of memory cells being connected in common with a same one of said third conductors, each third conductor corresponding to a respectively different set of memory cells in which each set includes one or more rows of memory cells;
• and
• means for selectively applying to said third conductors an information erasure signal, independently of said decoder circuit means, in response to an externally supplied address signal, in which simultaneous erasure of memory cells in a selected set is effected and said second conductors are kept from supplying a power potential to the first semiconductor regions of the field-effect transistor elements of the memory cells of said memory cell array in an erase mode.

A substantially rectangular semiconductor chip having an electrically erasable semiconductor nonvolatile memory device and a plurality of connection pads including address signal pads and I/O pads in a peripheral portion at a main surface of the chip, said semiconductor memory device comprising:

• at least one semiconductor memory cell array each having a plurality of nonvolatile memory cells arranged in rows and columns and a plurality of word line conductors and a plurality of data line conductors, each of said memory cells being connected with one word line conductor and one data line conductor, address signal pads for relatively higher order digits and those for relatively lower order digits being substantially arranged near one and the other of a first pair of opposing outer peripheral edges of the rectangular chip which are directioned substantially parallel with said word line conductors, respectively, each of said memory cells including a field-effect transistor element having a first gate electrode, a second gate electrode and drain and source regions formed in said chip, said second gate electrode being interposed between said first gate electrode and that part of the main surface of said chip, associated with each said field-effect transistor, which lies between said drain and source regions, said word line conductors being formed at the main surface of said chip and extended in a first direction substantially parallel with said rows, the first gate electrodes of field-effect transistor elements of memory cells on one row being connected in common with a respective one of said word line conductors, said data line conductors being formed at the main surface of said chip and extended in a second direction substantially parallel with said columns, the drain regions of field-effect transistor elements of memory cells on one column being connected in common with a respective one of said data line conductors, and erasure line conductors being formed at the main surface of said chip and extended in said first direction so as to be substantially parallel with said rows, the source regions of at least one row of field-effect transistor elements of memory cells being connected in common with a same one of said erasure line conductors, each erasure line conductor corresponding to a respectively different set of memory cells in which each set consists of one or more rows of memory cells;
• a row address decoder, for electrical connection with said address signal pads for relatively higher order digits, covering a first plan view area of the main surface of the chip, adjacent a first end side which is directioned substantially parallel with said data line conductors, of a second plan view area which is for said semiconductor memory cell array;
• a column address decoder, covering a third plan view area of the main surface of said chip in the vicinity of said semiconductor memory cell array and near that outer peripheral edge of said chip where said address signal pads for lower order digits are arranged for electrical connection therewith;
• erasure means, covering a fourth plan view area of the main surface of said chip adjacent a second end side of said second plan view area, for said semiconductor memory cell array, which second end side is opposite the first end side thereof and which is directioned substantially parallel with said data line conductors, provided for electrical connection with at least a portion of said address signal pads for relatively higher order digits for selectively applying an information erasure signal to said semiconductor memory cell array,
• wherein said erasure means selectively applies an information erasure signal to said erasure line conductors, independently of said row address decoder, in response to an externally supplied address signal, in which simultaneous erasure of memory cells in a selected set is effected and said data line conductors are kept from supplying a power potential to the drain regions of the field-effect transistor elements of memory cells of said at least one semiconductor memory cell array in an erase mode;
• and
• sense amplifier means, covering a fifth plan view area of the main surface of said chip adjacent that one of third and fourth opposite end sides of said second plan view area, for said semiconductor memory cell array, which is directioned substantially parallel with said word line conductors, near that outer peripheral edge of said chip where said I/O pads are arranged for electrical connection therewith.

An electrically erasable semiconductor nonvolatile memory device comprising:

• a memory array comprised of at least one memory cell array, each memory cell array including a plurality of memory cell blocks, each memory cell block including at least one column of nonvolatile memory cells, and each of said memory cells including a field-effect transistor element having a first gate electrode, first and second semiconductor regions, formed at a main surface of a semiconductor substrate, and a second gate electrode, said second gate electrode being interposed between said first gate electrode and that part of the main surface of said semiconductor substrate, associated with each said field-effect transistor element, which lies between said first and second semiconductor regions;
• first decoder circuit means for controlling said first gate electrodes of the field-effect transistors of said memory cells;
• first conductors formed over said semiconductor substrate and extended in a first direction corresponding to a row direction, the first gate electrodes of field-effect transistor elements of memory cells on one row being connected in common with a respective one of said first conductors;
• second conductors formed over said semiconductor substrate and extended in a second direction corresponding to a column direction, the first semiconductor regions of the field-effect transistor elements of memory cells on one column being connected in common with a respective one of said second conductors;
• and
• means selectively electrically connected, via said second conductors, with said at least one memory cell array for respectively supplying in an erase mode, independently of said decoder circuit means, information erasure voltages to at least a part of at least one of said memory cell blocks with relative time delays between said information erasure voltages,
• wherein said information erasure voltages are of a higher amplitude than voltages applied to the first gate electrodes of field-effect transistor elements in said at least part of said at least one memory cell block to be erased, and
• wherein the second semiconductor regions of field-effect transistor elements of the memory cells of said at least one memory cell array are continuously supplied with a same reference potential in the erase mode, and read and write modes of operation of said device.

An electrically erasable semiconductor nonvolatile memory device comprising:

• a plurality of memory blocks each including a plurality of memory cells arranged in rows and columns, each of said memory cells including a field-effect transistor (FET) element having a floating gate, a control gate and drain and source regions in which electric current flows between said drain and source regions of the FET element when the FET element is conductive, said memory blocks being arrayed in a direction parallel with a column direction;
• word lines each extending in a row direction, perpendicular to the direction of arraying of said memory blocks, and connected to the control electrodes of the FET elements of memory cells on one row, each of said memory blocks including at least one row of memory cells and at least one word line, said at least one word line of a memory block belonging to that memory block;
• data lines each of which is extended in a column direction and is electrically connected to the drain region of the FET elements of memory cells in a corresponding column;
• common source lines one provided for each of said memory blocks, the common source line in each memory block being connected in common with the source regions of the FET elements of memory cells included in that memory block;
• a decoder circuit responsive to an externally applied address signal for providing a predetermined voltage to the word lines included in a memory block selected among said plurality of memory blocks by the address signal;
• and
• an information erasure signal generating circuit responsive to said externally applied address signal for supplying an information erasure signal to the common source line included in the selected memory block,
• wherein the memory cells included in said selected memory block are simultaneously erased by providing a potential difference between said predetermined voltage on the word lines, provided by said decoder circuit, and a voltage of said information erasure signal, said information erasure signal being supplied to said common source line of the selected memory block independently of said decoder circuit, and the drain regions of the FET elements of the memory cells of the selected memory block are not supplied with a power potential in an erase mode.