Nonvolatile semiconductor memory device for storing multivalued data

A nonvolatile semiconductor memory device comprising:

• a memory element which is connected to a bit line and a word line and store s one of state “0”, state “1”, state “2”, and state “3” of data that differ in threshold voltage;
• a first storage circuit which is connected to said bit line and stores data of a first or a second logical level externally supplied;
• a second storage circuit which is connected to said bit line and stores the data of the first or second level read from said memory element;
• and
• a control circuit which controls not only the potential on said bit line and that on said word line but also the operation of said first and second storage circuits, wherein
• said control circuit operates i n such a manner that
• in a first operation, the control circuit changes the data in said memory element from state “0” to state “1” when the data in said first data storage circuit is data of the first logical level and keeps the data in said memory element at said state “0” when the data in said first storage circuit is data of the second logical level,
• that in a first verify operation of verifying whether said data has reached state “1”, the control circuit brings the data in said first storage circuit to the second logical level when the data in said first storage circuit is at the first logical level and said data has reached state “1”, keeps the data in said first storage circuit at the first logical level when said data has not reached state “1”, keeps the data in said first storage circuit at the second logical level when the data in said first storage circuit is at the second logical level, and carries out said first operation until the data in said first storage circuit has reached the second logical level,
• that in a second operation, the control circuit stores the data read from said memory element into said second storage circuit, changes the data in said memory element from state “1” to state “2” when the data in said first storage circuit is data of the first logical level externally supplied, changes the data in said memory element from state “0” to state “3” when the data in said memory element is in state “0”, and keeps the data in said memory element when the data in said first storage circuit is data of the second logical level,
• that in a second verify operation of verifying whether the data in said memory element has reached state “2”, the control circuit brings the data in said first storage circuit to the second logical level when the data has reached state “2” in a case where the data in said first storage circuit is at the first logical level and the data in said memory element is in state “1” before the second operation is carried out, keeps the data in said first storage circuit at the first logical level when said data has not reached state “2”, and brings the potential on the bit line to which the memory element is connected to the first logical level and the data in said first storage circuit to the first logical level when the data in said second storage circuit is at the second logical level in a case where the data in said memory element is in state “0” before said second operation is carried out, and
• that in a third verify operation of verifying said data has reached state “3”, the control circuit brings the data in said first storage circuit to the second logical level when the data in said first storage circuit is at the first logical level and said data has reached state “3”, keeps the data in said first storage circuit at the first logical level when said data has not reached state “3”, keeps the data in said first storage circuit at the second memory logical level when the data in said first storage circuit is at the second logical level, and carries out said second operation and second and third verify operations until the data in said first storage circuit has reached the second logical level.

A nonvolatile semiconductor memory device comprising:

• a memory element which is connected to a bit line and a word line and stores one of an n number of data items made up of state “0”, state “1”, . . . , state “n” (3≦n where n is a natural number);
• a data storage circuit which stores data of a first or a second logical level externally inputted;
• and
• a control circuit which controls not only the potential on said bit line and that on said word line but also the operation of said data storage circuit, wherein
• said control circuit, in a final write operation, charges state “0” of the smallest data stored in said memory element into state “n” of the largest data when the data in said first storage circuit is data of the first logical level externally supplied, and keeps the data in said memory element when the data in said first storage circuit is data of the second logical level.

A nonvolatile semiconductor memory device comprising:

• a memory element which is connected to a bit line and a word line and stores one of state “0”, state “1”, state “2”, and state “3” of data that differ in threshold voltage;
• a data storage circuit which is connected to said bit line and stores the data read from said memory element;
• and
• a control circuit which controls not only the potential on said bit line and that on said word line but also the operation of said data storage circuit, wherein
• said control circuit operates in such a manner that
• in a first read operation, the control circuit sets data of a first logical level in said data storage circuit when the data in said memory element is in either state “0” or state “1”, and sets data of a second logical level in said data storage circuit when the data in said memory element is in either state “2” or state “3”, and
• that in a second read operation, the control circuit sets data of the first logical level in said data storage circuit when the data in said memory element is in either state “0” or state “3”, and sets data of the second logical level in said data storage circuit when the data in said memory element is in either state “1” or state “2”.