Semiconductor memory device
AssigneeFujitsu Limited
InventorsTohru Takeshima, Kouichi Noro
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Abstract
A semiconductor memory device has a first ferroelectric memory cell in which data is written after the device is mounted on a board, and a second ferroelectric memory cell whose capacitance is larger than that of the first ferroelectric memory cell. This second ferroelectric memory cell is utilized as a memory cell in which cipher or the like are written in the fabrication process. The second ferroelectric memory cell is formed with a combination of a plurality of the first ferroelectric memory cells. In order to realize the second ferroelectric memory cell, word lines or plate lines corresponding to a plurality memory-cell rows may be short-circuited. Alternatively, bit lines corresponding to a plurality memory-cell columns may be short-circuited.
Claims9
A non-volatile ferroelectric semiconductor memory device comprising:
- a memory cell array having a plurality of first ferroelectric memory cells and a second ferroelectric memory cell which hold data by remanence, wherein said second ferroelectric memory cell has a larger capacitance than said first ferroelectric memory cell;
- a plurality of row selection lines by which said first ferroelectric cells and said second ferroelectric cells can be selected in the row direction in said memory cell array;
- and
- a plurality of column selection lines by which said first ferroelectric cells and said second ferroelectric cells can be selected in the column direction in said memory cell array,
- wherein said second ferroelectric memory cell is formed with a plurality of said first ferroelectric memory cells.
A non-volatile ferroelectric semiconductor memory device comprising:
- a memory cell array having a plurality of first ferroelectric memory cells and a second ferroelectric memory cell which hold data by remanence, wherein said second ferroelectric memory cell has a larger capacitance than said first ferroelectric memory cell;
- a plurality of row selection lines by which said first ferroelectric cells and said second ferroelectric cells can be selected in the row direction in said memory cell array;
- and
- a plurality of column selection lines by which said first ferroelectric cells and said second ferroelectric cells can be selected in the column direction in said memory cell array,
- wherein said first ferroelectric memory cell has a plurality of ferroelectric capacitors;
- and
- said second ferroelectric memory cell has such a configuration that a plurality of said ferroelectric capacitors, included in said first ferroelectric memory cell, are connected in parallel to each other.
A non-volatile ferroelectric semiconductor memory device comprising:
- a memory cell array having a plurality of first ferroelectric memory cells and a second ferroelectric memory cell which hold data by remanence, wherein said second ferroelectric memory cell has a larger capacitance than said first ferroelectric memory cells;
- a plurality of row selection lines by which said first ferroelectric memory cells and said second ferroelectric memory cell can be selected in the row direction in said memory cell array;
- and
- a plurality of column selection lines by which said first ferroelectric memory cells and said second ferroelectric memory cells can be selected in the column direction in said memory cell array,
- wherein said first ferroelectric memory cell has a plurality of ferroelectric capacitors;
- and
- said second ferroelectric memory cell has such a configuration that a plurality of said ferroelectric capacitors, included in adjacent memory cells of said first ferroelectric memory cells, are connected in parallel to each other.
Dependencies are inferred from the claim text.